參數(shù)資料
型號(hào): TLC320AC02C
廠商: Texas Instruments, Inc.
元件分類: DC/DC變換器
英文描述: RB Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 24V; Power: 1W; Low Cost 1W Converter; Power Sharing on Dual Output Version; Industry Standard Pinout; 1kVDC & 2kVDC Isolation Options; Optional Continuous Short Circuit Protected; UL94V-0 Package Material; Efficiency to 85%
中文描述: 單電源模擬接口電路
文件頁(yè)數(shù): 50/84頁(yè)
文件大小: 447K
代理商: TLC320AC02C
4–2
D15
D14
D13
D12
D11
D2
D1
D0
tf(SCLK)
0.8 V
SCLK
FS
tr(SCLK)
td(CH-FH)
td(CH-FL)
0.8 V
2 V
2 V
td(CH-DOUT)
D15
D14
D13
D12
D11
D2
D1
D0
tsu(DIN)
th(DIN)
DOUT
DIN
2 V
2 V
The time between falling edges of two primary FS signals is the conversion period.
The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
Figure 4–2. AIC Stand-Alone and Master-Mode Timing
D15
D14
D13
D12
D11
D2
D1
D0
2 V
2 V
tf(SCLK)
0.8 V
SCLK
FS
tr(SCLK)
tc(SCLK)
§
2 V
2 V
td(CH-DOUT)
D15
D14
D13
D12
D11
D2
D1
D0
tsu(DIN)
th(DIN)
DOUT
DIN
The time between falling edges of two primary FS signals is the conversion period.
The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
§The high-to-low transition of FS must must occur within
±
1/4 of a shift-clock period around the 2-V level of the shift clock
for the codec mode.
Figure 4–3. AIC Slave and Codec Emulation Mode
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