參數(shù)資料
型號: TLC32046M
廠商: Texas Instruments, Inc.
英文描述: Wide-Band Analog Interface Circuit
中文描述: 寬帶模擬接口電路
文件頁數(shù): 33/57頁
文件大小: 297K
代理商: TLC32046M
3–3
3.3.4
Receive Amplifier Input
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
A/D converter offset error (filters in)
10
70
mV
CMRR
Common-mode rejection ratio at IN+, IN–, or AUX
IN+, AUX IN–
See Note 6
55
dB
ri
Input resistance at IN+, IN– or
AUX IN+, AUX IN+, AUX IN–, REF
100
k
NOTE 6: The test condition is a 0-dBm, 1-kHz input signal with a 16-kHz conversion rate.
3.3.5
Transmit Filter Output
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
VOO
Output offset voltage at OUT+ or
OUT (single ended relative to
OUT– (single-ended relative to
ANLG GND)
TLC32046C, I
15
80
mV
TLC32046M
15
85
mV
Maximum peak output voltage
swing across RLat OUT+ or OUT
swing across RL at OUT+ or OUT–
(single-ended)
TLC32046C I
TLC32046C, I
RL
300
,
Offset voltage
= 0
±
3
V
VOM
Maximum peak output voltage
swing between OUT+ and OUT–
(differential output)
All typical values are at TA = 25
°
C.
3.3.6
Receive and Transmit Channel System Distortion, SCF Clock
Frequency = 288kHz (see Note 7)
RL
600
±
6
V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Attenuation of second harmonic of
A/D input signal
Single-ended
70
dB
Differential
VI=
VI = –0.1 dB to –24 dB
0 1 dB to
62
70
Attenuation of third and higher
harmonics of A/D input signal
Single-ended
65
dB
Differential
57
65
Attenuation of second harmonic of
D/A input signal
Single-ended
70
dB
Differential
VI=
VI = –0 dB to –24 dB
62
70
Attenuation of third and higher
harmonics of D/A input signal
Single-ended
Differential
65
65
dB
57
All typical values are at TA = 25
°
C.
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TLC32047 制造商:TI 制造商全稱:Texas Instruments 功能描述:Wide-Band Analog Interface Circuit
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TLC32047I 制造商:TI 制造商全稱:Texas Instruments 功能描述:Wide-Band Analog Interface Circuit