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參數(shù)資料
| 型號： | TLC2942PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK |
| 中文描述： | 高效能雙鎖相環(huán)積木 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大小： | 459K |
| 代理商： | TLC2942PW |
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
PCB layout considerations
The TLC2942I contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2942I user:
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC V
DD
and VCO V
DD
should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
VCO V
DD
to GND and LOGIC V
DD
to GND should be decoupled with a 0.1-
μ
F capacitor placed as close
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
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| TLC32041I | ANALOG INTERFACE CIRCUITS |
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