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參數(shù)資料
| 型號(hào)： | TLC2942IDBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 20 MHz, PDSO38 |
| 封裝： | PLASTIC, SO-38 |
| 文件頁(yè)數(shù)： | 19/29頁(yè) |
| 文件大小： | 473K |
| 代理商： | TLC2942IDBR |
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
PCB layout considerations
The TLC2942I contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2942I user:
D External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
D RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
D Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
D LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
D VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-F capacitor placed as close
as possible to the appropriate device terminals.
D The no-connection (NC) terminal on the package should be connected to GND.
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