- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383953 > TLC2933PW (Texas Instruments, Inc.) HIGH-PERFORMANCE PHASE-LOCKED LOOP PDF資料下載
參數(shù)資料
| 型號(hào)： | TLC2933PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| 中文描述： | 高性能鎖相環(huán) |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 367K |
| 代理商： | TLC2933PW |
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
gain of VCO and PFD
Figure 16 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The K
p
and K
V
values are obtained from the operating
characteristics of the device as shown in
Figure 16. K
p
is defined from the phase detector
V
OL
and V
OH
specifications and the equation
shown in Figure 16(b). K
V
is defined from
Figures 8, 9, 10, and 11 as shown in Figure 16(c).
The parameters for the block diagram with the
units are as follows:
K
V
: VCO gain (rad/s/V)
K
p
: PFD gain (V/rad)
K
f
: LPF gain (V/V)
K
N
: countdown divider gain (1/N)
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
R
BIAS
The external bias resistor sets the VCO center frequency with 1/2 V
DD
applied to the VCO IN terminal. For the
most accurate results, a metal-film resistor is the better choice but a carbon-composition resistor can also be
used with excellent results. A 0.22
μ
F capacitor should be connected from the BIAS terminal to ground as close
to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 17 is as follows:
H
0.8 Kp
KV
Kf(
)
Where
K
f
(
∞
) = the filter transfer function value at
ω
=
∞
(1)
Divider
(KN = 1/N)
PFD
(Kp)
VCO
(KV)
LPF
(Kf)
TLC2933
f REF
VOH
fMAX
fMIN
VIN MIN
VIN MAX
–2
π
2
π
–
π
0
π
Range of
Comparison
VOH
VOL
Kp =
VOH – VOL
4
π
KV =
2
π
(fMAX – fMIN)
VIN MAX – VIN MIN
(c)
Figure 16. Example of a PLL Block Diagram
(a)
(b)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC2933PWLE | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| TLC2942PW | HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK |
| TLC32040C | ANALOG INTERFACE CIRCUITS |
| TLC32040I | ANALOG INTERFACE CIRCUITS |
| TLC32041C | ANALOG INTERFACE CIRCUITS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC2934IPW | 功能描述:相位探測(cè)器 / 移相器 High Perform Sngl Locked Loop RoHS:否 制造商:M/A-COM Technology Solutions 封裝 / 箱體:PQFN-24 封裝:Reel |
| TLC2934IPWG4 | 功能描述:相位探測(cè)器 / 移相器 High Perform Sngl Locked Loop RoHS:否 制造商:M/A-COM Technology Solutions 封裝 / 箱體:PQFN-24 封裝:Reel |
| TLC2934IPWR | 功能描述:相位探測(cè)器 / 移相器 Hi Perf Sngl Phase Locked Loop RoHS:否 制造商:M/A-COM Technology Solutions 封裝 / 箱體:PQFN-24 封裝:Reel |
| TLC2934IPWRG4 | 功能描述:IC PHASE LOCK LOOP HP 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| TLC2940IPW | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。