參數(shù)資料
型號(hào)： TLC2932PW
廠商： Texas Instruments, Inc.
英文描述： HIGH-PERFORMANCE PHASE-LOCKED LOOP
中文描述： 高性能鎖相環(huán)
文件頁(yè)數(shù)： 16/24頁(yè)
文件大?。?/td> 418K
代理商： TLC2932PW
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should be
consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shown
in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-B because
of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO
input. The value of C2 should be equal to or less than one tenth the value of C1.
R1
C1
T1 = C1R1
(a) LAG FILTER
R1
C1
T1 = C1R1
T2 = C1R2
R2
(b) LAG-LEAD FILTER
R2
C1
R1
T1 = C1R1
T2 = C1R2
(c) ACTIVE FILTER
A
–
VI
VO
VI
VO
VI
C2
VO
C2
Figure 25. LPF Examples for PLL
the passive filter
The transfer function for the lag-lead filter shown in Figure 25(b) is;
VO
VIN
1
s
(T1
T2
1
s
T2)
Where
T1
R1
C1 and T2
R2
C1
Using this filter makes the closed loop PLL system a second-order type 1 system. The response curves of this
system to a unit step are shown in Figure 26.
the active filter
When using the active integrator shown in Figure 25(c), the phase detector inputs must be reversed since the
integrator adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B
terminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 25(c) is:
F(s)
1
s
R2
C1
s
R1
C1
Using this filter makes the closed loop PLL system a second-order type 2 system. The response curves of this
system to a unit step are shown in Figure 27.
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
相關(guān)PDF資料
PDF描述
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TLC2933AIPW 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
TLC2933AIPWG4 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
TLC2933AIPWR 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
TLC2933AIPWRG4 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
TLC2933IPW 功能描述:鎖相環(huán) - PLL Phase Locked Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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