參數(shù)資料
型號(hào): TLC2574IDW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, SOP-20
文件頁(yè)數(shù): 46/49頁(yè)
文件大小: 1137K
代理商: TLC2574IDW
TLC3574, TLC3578, TLC2574, TLC2578
5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL
SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS
SLAS262C OCTOBER 2000 REVISED MAY 2003
6
WWW.TI.COM
general electrical characteristics over recommended operating free-air temperature range, single-
ended input, normal long sampling, 200 KSPS, AVDD = 5 V, VREFP = 4 V, VREFM = 0 V,
SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source
resistance = 25
(unless otherwise noted)
TLC3574/78 and TLC2574/78
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
bits
Analog Input
Voltage range
10
V
Selected analog input channel bias current
Selected channel at 10 V
0.8
1.6
mA
Selected analog input channel bias current
Selected channel at –10 V
1.6
1.2
mA
Impedance
10
k
Capacitance
30
pF
Reference
VREFP
Positive reference voltage
3.96
4
4.04
V
VREFM
Negative reference voltage
0
AGND
V
Input impedance
No conversion (AVDD = 5V, CS= DVDD,
SCLK=DGND)
100
M
Input impedance
Normal long sampling (AVDD = 5V, CS=DGND,
SCLK = 25 MHz, External conversion clock)
8.3
12.5
k
No conversion (AVDD = 5 V,
SCLK = DGND, CS = DVDD)
1.5
A
Reference current
Normal long sampling (AVDD = 5 V, CS = DGND,
External conversion clock, SCLK = 25 MHz,
VREF = 5 V)
0.4
0.6
mA
Internal oscillation frequency
DVDD = 2.7 V – 5.5 V
6.5
MHz
Internal OSC, 6.5 MHz minimum
TLC3574/78
2.785
t(conv)
Conversion time
Internal OSC, 6.5 MHz minimum
TLC2574/78
2.015
S
t(conv)
Conversion time
Conversion clock is external source,
TLC3574/78
2.895
S
Conversion clock is external source,
SCLK = 25 MHz (see Note 1)
TLC2574/78
2.095
Acquisition time
Normal short sampling
1.2
S
Throughput rate (see Note 2)
Normal long sampling, fixed channel
in mode 00 or 01
200
KSPS
All typical values are at TA = 25°C.
NOTES:
1. Conversion time t(conv) is (18 × 4 × SCLK) + 15 ns for TLC3574/78. Conversion time is (13 × 4 × SCLK) + 15 ns for TLC2574/78.
2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC.
相關(guān)PDF資料
PDF描述
TLC3574IDW 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLC2578IPW 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3574IDWRG4 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLC2578IPWRG4 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3578IDWG4 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
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