參數(shù)資料
型號: TLC2552CDGK
廠商: Texas Instruments
文件頁數(shù): 3/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT DUAL LOW-PWR 8-MSOP
產(chǎn)品培訓模塊: Data Converter Basics
標準包裝: 80
位數(shù): 12
采樣率(每秒): 400k
數(shù)據(jù)接口: DSP,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 15mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-MSOP
包裝: 管件
輸入數(shù)目和類型: 1 個單端,單極
配用: 296-20572-ND - EVAL MOD FOR TLC2552
296-18350-ND - KIT 5-6K INTERFACE BOARD
TLC2551, TLC2552, TLC2555
5-V, LOW-POWER, 12-BIT, 175/360 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D – MARCH 2000 – REVISED MAY 2003
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ac specifications (fi = 20 kHz)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SINAD
Signal-to-noise ratio + distortion
400 KSPS, VDD = VREF = 5 V
70
72
dB
THD
Total harmonic distortion
400 KSPS, VDD = VREF = 5 V
–84
–80
dB
ENOB
Effective number of bits
400 KSPS, VDD = VREF = 5 V
11.8
bits
SFDR
Spurious free dynamic range
400 KSPS, VDD = VREF = 5 V
–84
–80
dB
Analog Input
Full-power bandwidth, –3 dB
1
MHz
Full-power bandwidth, –1 dB
500
kHz
external reference specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference input voltage
VDD = 4.5 V to 5.5 V
2
VDD
V
Reference input impedance
V5 5 V
CS = 1,
SCLK = 0
100
M
Reference input impedance
VDD = 5.5 V
CS = 0,
SCLK = 20 MHz
20
25
k
Reference current
VDD = VREF = 5.5 V
100
400
A
Reference input capacitance
VV
5 5 V
CS = 1,
SCLK = 0
5
15
pF
Reference input capacitance
VDD = VREF = 5.5 V
CS = 0,
SCLK = 20 MHz
20
45
50
pF
VREF
Reference voltage
VDD = 4.5 V to 5.5 V
VDD
V
dc specification, VDD = VREF = 4.5 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INL
Integral linearity error (see Note 4)
±0.6
±1
LSB
DNL
Differential linearity error
See Note 3
±0.5
±1
LSB
E
Offset error (see Note 5)
See Note 3
TLC2551/52
±1.5
LSB
EO
Offset error (see Note 5)
See Note 3
TLC2555
±2.5
LSB
E
Gain error (see Note 5)
See Note 3
TLC2551/52
±2
LSB
EG
Gain error (see Note 5)
See Note 3
TLC2555
±5
LSB
E
Total unadjusted error (see Note 6)
See Note 3
TLC2551/52
±2
LSB
Et
Total unadjusted error (see Note 6)
See Note 3
TLC2555
±5
LSB
NOTES:
3. Analog input voltages greater than that applied to VREF convert as all ones (111111111111).
4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage.
6. Total unadjusted error comprises linearity, zero, and full-scale errors.
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