參數(shù)資料
型號(hào): TLC2543-EVM
廠商: Texas Instruments, Inc.
英文描述: TLC2543 Evaluation Module(TLC2543評(píng)估板)
中文描述: 器TLC2543評(píng)估模塊(器TLC2543評(píng)估板)
文件頁(yè)數(shù): 30/52頁(yè)
文件大小: 231K
代理商: TLC2543-EVM
Driving the Input of a Switched-Capacitor ADC
2-16
2.7
Driving the Input of a Switched-Capacitor ADC
When applying an analog signal to the input of a switched-capacitor ADC such
as the TLC2543, care must be taken to provide a low enough impedance to
the input terminal to charge the internal capacitor (see Figure 2–3) enough for
an accurate conversion during the sampling phase of the converter. The sam-
pling time depends on the period of the I/O clock rate being used to drive the
converter and the number of transfer bits commanded. With the maximum I/O
clock frequency of 4.1 MHz and a 12-bit transfer mode, the TLC2543 uses
eight clock cycles (or approximately 2
μ
s) for the sampling time.
Figure 2–3.Equivalent Input Circuit
V
S
C1
60 pF (max)
R1
1 k
R
S
Driving
Source
TLC2543 Equivalent Input Circuit
V
C
The input equivalent circuit of the TLC2543 looks like a series resistance and
a capacitor to ground during sampling and an open circuit during conversion.
For accurate operation the input capacitor must be charged to the required
accuracy of 1/2 LSB (or more, depending on the required system error budget)
during the sampling phase of the ADC cycle.
The voltage on capacitor C1 is given by:
V
C
V
S
1–e
t TC
(1)
Where:
TC = the time constant C1(R
S
+R1)
The final voltage value of V
C
within 1/2 LSB of V
S
is given by:
V
S
2n
Where:
n = the resolution of the converter.
V
C
1 2 LSB
V
S
1
(2)
Equating equation 1 to equation 2, then:
V
S
V
S
2n
1
V
S
1
e
t TC
(3)
Therefore, the charging time in terms of the circuit time constants is:
t 1 2 LSB
TC ln 2n
1
(4)
For a 12-bit converter, this would be:
t
S
TC x ln(8192)
9TC
(5)
The internal capacitance for the TLC2543 is 60 pF maximum and the internal
series resistance is 1 k
. Therefore, with an I/O clock at 4.1 MHz and a 12-bit
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