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參數(shù)資料
| 型號(hào)： | TLC157R |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EPROM/ROM-Based 8-Bit Microcontroller Series |
| 中文描述： | 存儲(chǔ)器/基于ROM的8位微控制器系列 |
| 文件頁數(shù)： | 15/50頁 |
| 文件大?。?/td> | 552K |
| 代理商： | TLC157R |
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2.1.16 OPTION Register
Address
N/A (w)
By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register.
The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the
Timer0/WDT prescaler, Timer0, and the external INT interrupt.
The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.
PS2:PS0
: Prescaler rate select bits.
PS2:PS0
Timer0 Rate
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1:256
PSA
: Prescaler assign bit.
= 1, WDT (watch-dog timer).
= 0, TMR0 (Timer0).
T0SE
: TMR0 source edge select bit.
= 1, Falling edge on T0CKI pin.
= 0, Rising edge on T0CKI pin.
T0CS
: TMR0 clock source select bit.
= 1, External T0CKI pin.
= 0, internal instruction clock cycle.
INTEDG
:
Interrupt edge select bit.
= 1, interrupt on rising edge of INT pin.
= 0, interrupt on falling edge of INT pin.
Bit7
: Not used.
2.1.17 IOSTA, IOSTB & IOSTC (Port I/O Control Registers)
Address
Name
B7
B6
B5
N/A (w)
IOSTA
Port A I/O Control Register
N/A (w)
IOSTB
Port B I/O Control Register
N/A (w)
IOSTC
Port C I/O Control Register
The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (05h~07h)
instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode).
A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins (output mode).
The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.
Name
OPTION
B7
-
B6
B5
T0CS
B4
T0SE
B3
PSA
B2
PS2
B1
PS1
B0
PS0
INTEDG
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:2
1:4
1:8
1:16
1:32
1:64
1:128
B4
B3
B2
B1
B0
TLC
TLC156
Rev0.95 Nov 20, 2003
P.2/TLC156
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