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1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the
operation of the device.
In TLC157, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to be configured for the desired bank.
TABLE 1.1: Operational Registers Map
Address
Name
B7
B6
B5
N/A (w)
OPTION
-
INTEDG
T0CS
N/A (w)
IOSTA
Port A I/O Control Register
N/A (w)
IOSTB
Port B I/O Control Register
N/A (w)
IOSTC
Port C I/O Control Register
00h (r/w)
INDF
Uses contents of FSR to address data memory (not a physical register)
01h (r/w)
TMR0
8-bit real-time clock/counter
02h (r/w)
PCL
03h (r/w)
STATUS
GP2
GP1
GP0
04h (r/w)
FSR
RP1
(3)
RP0
(3)
05h (r/w)
PORTA
-
-
-
06h (r/w)
PORTB
IOB7
IOB6
IOB5
07h (r/w)
PORTC
(1)
IOC7
IOC6
IOC5
08h (r/w)
PCON
WDTE
EIS
LVDTE
09h (r/w)
WUCON
WUB7
WUB6
WUB5
0Ah (r/w)
PCHBUF
(2)
-
-
-
0Bh (r/w)
PDCON
/PDB3
/PDB2
/PDB1
0Ch (r/w)
ODCON
ODB7
ODB6
ODB5
0Dh (r/w)
PHCON
/PHB7
/PHB6
/PHB5
0Eh (r/w)
INTEN
GIE
-
-
0Fh (r/w)
INTFLAG
-
-
-
Legend: - = unimplemented, read as ‘0’,
Note 1 : PORTC is an 8-bit I/O Register for TLC155/157.
PORTC is a General Purpose Register for TLC154/156.
2 : There is only 1 bit in TLC154/155. There are only 2 bits in TLC156. And there are 3 bits in
TLC157.
3 : For TLC154/155/156, these bits are not used, read as ‘1’
B4
T0SE
B3
PSA
B2
PS2
B1
PS1
B0
PS0
Low order 8 bits of PC
TO
Indirect data memory address pointer
-
IOA3
IOB4
IOB3
IOC4
IOC3
ROC
-
WUB4
WUB3
-
-
/PDB0
/PDA3
ODB4
ODB3
/PHB4
/PHB3
-
-
-
-
PD
Z
DC
C
IOA2
IOB2
IOC2
-
WUB2
Upper 3 bits Buffer of PC
/PDA2
/PDA1
ODB2
ODB1
/PHB2
/PHB1
INTIE
PBIE
INTIF
PBIF
IOA1
IOB1
IOC1
-
WUB1
IOA0
IOB0
IOC0
-
WUB0
/PDA0
ODB0
/PHB0
T0IE
T0IF
TLC
TLC156
Rev0.95 Nov 20, 2003
P.2/TLC156