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參數資料
| 型號： | TL16C554I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| 中文描述： | 異步通信元 |
| 文件頁數： | 29/33頁 |
| 文件大小： | 478K |
| 代理商： | TL16C554I |
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
reset
After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an
idle mode until initialization. A high on RESET causes the following:
1.
It initializes the transmitter and receiver internal clock counters.
2.
It clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE),
which are set. The MCR is also cleared. All of the discrete lines, memory elements, and miscellaneous logic
associated with these register bits are also cleared or turned off. The LCR, divisor latches, RBR, and
transmitter buffer register are not affected.
RXRDY operation
In mode 0, RXRDY is asserted (low) when the receive FIFO is not empty; it is released (high) when the FIFO
is empty. In this way, the receiver FIFO is read when RXRDY is asserted (low).
In mode 1, RXRDY is asserted (low) when the receive FIFO has filled to the trigger level or a character time-out
has occurred (four character times with no transmission of characters); it is released (high) when the FIFO is
empty. In this mode, multiple received characters are read by the DMA device, reducing the number of times
it is interrupted.
RXRDY and TXRDY outputs from each of the four internal ACEs of the TL16C554 are ANDed together
internally. This combined signal is brought out externally to RXRDY and TXRDY.
Following the removal of the reset condition (RESET low), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bits in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 12.
Table 12. RESET Affects on Registers and Signals
REGISTER/SIGNAL
Interrupt enable register
RESET CONTROL
Reset
RESET STATE
All bits cleared (0–3 forced and 4–7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Bits 4–5 are permanently cleared
All bits cleared
All bits cleared (5–7 permanent)
All bits cleared
All bits cleared, except bits 5 and 6 are set
Bits 0–3 cleared, bits 4–7 input signals
High
Low
Low
Low
Low
High
Interrupt identification register
Reset
Line control register
Modem control register
FIFO control register
Line status register
Modem status register
TXx
Interrupt (RCVR ERRS)
Interrupt (receiver data ready)
Interrupt (THRE)
Interrupt (modem status changes)
RTS
Reset
Reset
Reset
Reset
Reset
Reset
Read LSR/Reset
Read RBR/Reset
Read IIR/Write THR/Reset
Read MSR/Reset
Reset
DTR
Reset
High
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相關代理商/技術參數 |
參數描述 |
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| TL16C554IFN | 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554IFNG4 | 功能描述:UART 接口集成電路 Quad UART w/16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554IFNR | 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554IFNRG4 | 功能描述:UART 接口集成電路 Quad UART w/16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554IPN | 功能描述:UART 接口集成電路 Qd UART w/16b FIFO RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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