參數(shù)資料
型號(hào)： TL16C554AI
廠商： Texas Instruments, Inc.
英文描述： ASYNCHRONOUS-COMMUNICATIONS ELEMENT
中文描述： 異步通信元
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 605K
代理商： TL16C554AI
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
–
AUGUST 2001
–
REVISED JULY 2003
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
line-control register (LCR) (continued)
Word-Length
Select
0
0
1
1
0 = 5 Data Bits
1 = 6 Data Bits
0 = 7 Data Bits
1 = 8 Data bits
LINE CONTROL REGISTER
LCR
7
LCR
6
LCR
5
LCR
4
LCR
3
LCR
2
LCR
1
LCR
0
Stop-Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Even-Parity
Select
0 = Odd Parity
1 = Even Parity
Stick Parity
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Break Control
0 = Break Disabled
1 = Break Enabled
Divisor-Latch
Access BIt
0 = Access Receiver Buffer
1 = Access Divisor Latches
Figure 18. Line-Control Register Contents
line-status register (LSR)
The LSR is a single register that provides status indicators. The LSR shown in Table 6 is described in the
following bulleted list:
Bit 0: LSR0 is the data ready (DR) bit. Data ready is set when an incoming character is received and
transferred to the receiver-buffer register or to the FIFO. LSR0 is cleared by a CPU read of the data in the
receiver-buffer register or in the FIFO.
Bit 1: LSR1 is the overrun error (OE) bit. An overrun error indicates that data in the receiver-buffer register
is not read by the CPU before the next character is transferred to the receiver-buffer register, therefore
overwriting the previous character. The OE indicator is cleared whenever the CPU reads the contents of
the LSR. An overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely
received. The overrun error is detected by the CPU on the first LSR read after it occurs. The character in
the shift register is not transferred to the FIFO, but it is overwritten.
Bit 2: LSR2 is the parity error (PE) bit. A parity error indicates that the received data character does not
have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error
and is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated
with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.
Bit 3: LSR3 is the framing error (FE) bit. A framing error indicates that the received character does not have
a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero
bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO
mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when
the character is at the top of the FIFO.
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參數(shù)描述
TL16C554AIFN 功能描述:UART 接口集成電路 Quad UART w/ 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C554AIFNR 功能描述:UART 接口集成電路 Quad UART w/ 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C554AIPN 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C554AIPNG4 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C554AIPNR 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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