
January 1999 TOKO, Inc.
Page 7
TK75001
PIN DESCRIPTIONS
SUPPLY VOLTAGE PIN (V
CC
)
This pin is connected to the supply voltage. The IC is in a
low current (500
μ
A typ.) standby mode before the supply
voltage exceeds 14.5 V (typ.), which is the upper threshold
of the UVLO circuit. The IC switches back to standby mode
when the supply voltage drops below 10.5 V (typ.). An
internal clamp limits the peak supply voltage to about 17.5
V (typ.). The absolute maximum supply voltage from a low
impedance source is 16 V. The device is always guaranteed
to turn on before the internal clamp turns on.
GROUND PIN (GND)
This pin provides ground return for the IC.
DRIVE PIN (DRV)
This pin drives the external MOSFET with a totem pole
output stage capable of sinking or sourcing a peak current
of about 1 A. In standby mode, the drive pin can sink about
5 mA while keeping the drive pin pulled down to about 1 V.
The maximum duty cycle of the output signal is typically
44%.
TIMING CAPACITOR PIN (C
T
)
The external timing capacitor is connected to the C
pin.
That capacitor is the only component needed for setting
the clock frequency. The frequency measured at the C
pin
is twice the frequency measured at the DRV Pin. The
maximum recommended clock frequency of the device is
1.6 MHz. At normal operation, during the rising section of
the timing-capacitor voltage, a trimmed internal current of
205
μ
A flows out from the C
pin and charges the capacitor.
During the falling section of the timing-capacitor voltage an
internal current of about 1.8 mA discharges the capacitor.
If the voltage at the feedback(FB) pin exceeds 1.35 V (e.g.,
due to the turnoff delay during a short-circuit at the output
of a converter using the IC), the charging current is
reduced to about 59
μ
A, leading to a 2.17-fold reduction in
switching frequency. The frequency reduction is useful for
preventing short-circuit current runaway.
FEEDBACK PIN (FB)
The feedback pin receives the sum of three signals: the
error signal (from the external error amplifier), the switch
current signal and a voltage ramp generated across the
terminating resistance by an internal sawtooth-shaped
current with a peak value of about 200
μ
A. The error signal
is needed for stabilizing the output voltage or current. The
switch current signal is needed in current-mode controlled
converters and in converters with cycle-by-cycle overload
protection. Also, the switch current signal is required for
detecting impending short-circuit current runaway, and for
initiating a frequency reduction for preventing the runaway.
The voltage ramp is needed for slope compensation in
current-mode controlled converters, or for pulse-width
modulation in voltage-mode controlled converters.
At higher clock frequencies, the bandwidth limitation of the
internally-generated sawtooth-shaped current source
becomes more apparent. The degree to which ramp
bandwidth is tolerable depends on performance
requirements at narrow pulse widths. A low impedance at
the feedback pin can effectively eliminate the internally-
generated ramp effects, and an external ramp can be
readily created to attain higher performance at high
frequencies, if desired.