參數(shù)資料
型號: TISP9110LDM
廠商: Bourns Inc.
英文描述: INTEGRATED COMPLEMENTARY BUFFERED-GATE SCRS FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION
中文描述: 集成了基于互補緩沖,門沙特遙感中心的雙極用戶接口過電壓保護
文件頁數(shù): 2/5頁
文件大?。?/td> 194K
代理商: TISP9110LDM
AUGUST 2004 – REVISED FEBRUARY 2005
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
Absolute Maximum Ratings, TA = 25
°
C (Unless Otherwise Noted)
TISP9110LDM Overvoltage Protector
Electrical Characteristics for any Section, TA = 25
°
C (Unless Otherwise Noted)
Parameter
Test Conditions
Min
Typ
Max
-5
-50
+5
+50
-5
+5
-15
-11
+15
+11
Unit
I
D
Off-state current
V
D
= V
DRM
, V
G1(Line)
= 0, V
G2
+5 V
V
D
= V
DRM
, V
G2(Line)
= 0, V
G1
-5 V
T
A
= 25
°
C
T
A
= 85
°
C
T
A
= 25
°
C
T
A
= 85
°
C
μ
A
I
G1(Line)
I
G2(Line)
Negative-gate leakage current
Positive-gate leakage current
V
G1(Line)
= -220 V
V
G2(Line)
= +220 V
V
G1
= -100 V, I
T
= -100 A (see Note 6)
V
G1
= -100 V, I
T
= -30 A
V
G2
= +100 V, I
T
= +100 A (see Note 6)
V
G2
= +100 V, I
T
= +30 A
V
G1
= -60 V, I
T
= -1 A, di/dt = 1 A/ms
I
T
= -5 A, t
p(g)
20
μ
s, V
G1
= -60 V
I
T
= 5 A, t
p(g)
20
μ
s, V
G2
= 60 V
f = 1 MHz, V
D
= -3 V, G1 & G2 open circuit
μ
A
μ
A
V
G1L(BO)
Gate - Line impulse breakover voltage
2/10
μ
s
10/1000
μ
s
2/10
μ
s
10/1000
μ
s
V
V
G2L(BO)
Gate - Line impulse breakover voltage
V
I
H
-
I
G1T
I
G2T
C
O
Negative holding current
Negative-gate trigger current
Positive-gate trigger current
Line - Ground off-state capacitance
-150
mA
mA
mA
pF
+5
-5
32
NOTE:
6. Voltage measurements should be made with an oscilloscope with limited bandwidth (20 MHz) to avoid high frequency noise.
Rating
Symbol
Value
Unit
Repetitive peak off-state voltage
V
G1(Line)
= 0, V
G2
+5 V
V
G2(Line)
= 0, V
G1
-5 V
Non-repetitive peak impulse current (see Notes 1, 2, 3 and 4)
2/10
μ
s (Telcordia GR-1089-CORE)
5/310
μ
s (ITU-T K.20, K.21 & K.45, K.44 open-circuit voltage wave shape 10/700
μ
s)
10/1000
μ
s (Telcordia GR-1089-CORE)
Non-repetitive peak on-state current, 50 Hz / 60 Hz (see Notes 1, 2, 3 and 5)
0.2 s
1 s
900 s
Maximum negative battery supply voltage
Maximum positive battery supply voltage
Maximum differential battery supply voltage
Junction temperature
Storage temperature range
V
DRM
-120
+120
V
I
PPSM
±
100
±
45
±
30
A
I
TSM
9.0
5.0
1.7
-110
+110
220
A
V
G1M
V
G2M
V
(BAT)M
T
J
T
stg
V
V
V
°
C
°
C
-40 to +150
-65 to +150
NOTES: 1. Initially the device must be in thermal equilibrium with T
J
= 25
°
C. The surge may be repeated after the device returns to its initial
conditions.
2. The rated current values may be applied to either of the Line to Ground terminal pairs. Additionally both terminal pairs may have
their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of a
single terminal pair).
3. Rated currents only apply if pins 6 & 7 (Ground) are connected together.
4. Applies for the following bias conditions: V
G1
= -20 V to -110 V, V
G2
= 0 V to +110 V.
5. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm
printed wiring track widths.
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