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參數資料
| 型號： | TIBPAL20R8-7MJT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Adjustable 2.5-36V +/-0.4% Tolerance, 1-100mA Shunt Regulator; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50 |
| 中文描述： | 高性能影響X PAL制式電路 |
| 文件頁數： | 18/35頁 |
| 文件大?。?/td> | 439K |
| 代理商： | TIBPAL20R8-7MJT |
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TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M TIBPAL20R4-7M TIBPAL20R6-7M TIBPAL20R8-7M
HIGH-PERFORMANCE
IMPACT-X
PAL
CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
18
f
max
SPECIFICATIONS
f
max
without feedback, see Figure 3
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t
su
+ t
h
).
However, the minimum fmax is determined by the minimum clock period (t
w
high + t
w
low).
Thus, fmaxwithout feedback
(twhigh
1
twlow) or
1
(tsu
th).
CLK
Logic
Array
tsu + th
or
tw high + tw low
C1
1D
Figure 3. f
max
Without Feedback
f
max
with internal feedback, see Figure 4
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, fmaxwith internal feedback
1
(tsu
tpdCLK
to
FB).
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
Logic
Array
tsu
tpd CLK-to-FB
C1
1D
Figure 4. f
max
With Internal Feedback
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