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參數(shù)資料
| 型號： | TIBPAL20R3 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS |
| 中文描述： | 高性能影響X PAL制式電路 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 292K |
| 代理商： | TIBPAL20R3 |
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE
IMPACT-X
PAL
CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
15
PARAMETER MEASUREMENT INFORMATION
tsu
S1
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3.5 V
0.3 V
1.5 V
1.5 V
th
1.5 V
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
1.5 V
1.5 V
1.5 V
1.5 V
tw
1.5 V
1.5 V
≈
3.3 V
VOL
VOH
VOH –0.5 V
≈
0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
R1
VOL
+
0.5 V
5 V
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
From Output
Under Test
Test
Point
Input
Out-of-Phase
Output
(see Note D)
Timing
Input
Data
Input
In-Phase
Output
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR
≤
1 MHz, tr = tf
≤
2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
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