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參數(shù)資料
| 型號(hào)： | THS7319IZSVT |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 17/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EDTV VIDEO AMP 3CH 9-UCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 緩沖器 |
| 輸出類型： | 滿擺幅 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 20MHz |
| 轉(zhuǎn)換速率： | 80 V/µs |
| 電流 - 電源： | 3.4mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 9-UltraCSP?（Xcept） |
| 供應(yīng)商設(shè)備封裝： | 9-UCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 863 (CN2011-ZH PDF) |
| 其它名稱： | 296-24604-6 |
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MinSpace S
T TraceWidth
MetalDiameter
SeeDimension
or
A
C
X Pitch
Y Pitch
SBOS468A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
(1) Circuit traces from the NSMD-defined PWB lands should be 75-
m to 100-m wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand-off and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is greater than the operating temperature range
of the intended application.
(3) For a PWB using a Ni/Au surface-finish, the Au thickness should be less than 0.5
m to avoid a reduction in thermal fatigue performance.
(4) Solder mask thickness should be less than 20
m above the copper circuit pattern.
(5) Best solder stencil performance is achieved using laser-cut stencils with electro-polishing. Use of chemically-etched stencils results in
inferior solder-paste volume control.
(6) Trace routing away from the MicrostarCSP device should be balanced in X and Y directions to avoid unintentional component movement
because of solder wetting forces.
Figure 54. Trace Width/Spacing Example
Table 3. Definitions for Figure 54
(S or T) TRACE
PAD
PACKAGE PITCH
(A or C) METAL DIAMETER
WIDTH/SPACING
NSMD
0.50 mm
0.25 mm
0.08 mm
24
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): THS7319
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