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參數(shù)資料
| 型號： | THMC45DGNR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, PDSO8 |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 255K |
| 代理商： | THMC45DGNR |
THMC45
5V AND 3.3V DC BRUSHLESS FAN MOTOR DRIVER
WITH SINGLE WIRE CONTROL
SLIS101A MAY 2001
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
tachometer signaling on PWM input (PWM)
The PWM terminal of the THMC45 provides a 1-
s (typical) current sink pulse, t(PW), following the next rising
edge of the PWM input signal after the Hall sensor amplifier changes states (see Figure 4). Note that the
THMC45 incorporates a blanking circuit that disregards transitions on the PWM terminal during the TACH
current pulses. This ensures that the TACH pulses do not corrupt the output PWM signal. This current signal
can be detected with external circuitry and can be sent to the TACH input of the hardware monitor portion of
a Super I/O device.
t(de-glitch)
td
t(PW)
t(de-glitch)
Differential Hall
Signal (H+ H)
Conditioned Hall
Amplifier Output
(Internal)
PWM Input
TACH Current
Sink Pulses
TACH
Figure 4. Tachometer Current Pulse Timing on PWM Input Pin
sleep/run states using PWM input (PWM)
The THMC45 enters a low-current sleep state when the PWM input maintains a logic low level for more than
2 ms (typical), t(SLEEP). In sleep state, the OUTA and OUTB outputs are in a high-impedance state. The THMC45
transitions from sleep state to run state on the first rising edge on the PWM input. Figure 5 shows the timing
relationships between the PWM signal and sleep/run state.
t(SLEEP)
PWM Input
OUTA, OUTB
Enable Signal
t(PWM_de-glitch)
Figure 5. PWM Input Signal, Sleep State, and Run State Timing
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