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參數(shù)資料
| 型號： | THC63LVD824 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single(135MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA |
| 中文描述： | 單（135MHz）/雙（170MHz的）鏈接的LVDS接收器的XGA / SXGA / SXGA /的UXGA |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 227K |
| 代理商： | THC63LVD824 |
THC63LVD823_Rev2.0
Copyright 2000-2003 THine Electronics, Inc. All rights reserved 1
THine Electronics, Inc.
THC63LVD823
Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA
General Description
The THC63LVD823 transmitter is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions.
The THC63LVD823 converts 48bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin.
In Single Link, the transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, the transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Features
Wide dot clock range: 25-135MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
PLL requires No external components
Supports Dual Link, Dual-in (TTL)/Dual-out
(LVDS) pixel up to 170MHz dot clock for UXGA
Supports Single Link, Dual-in (TTL)/Single-out
(LVDS) pixel up to 135MHz dot clock for SXGA+
Supports Single Link, Single-in (TTL)/Single-out
(LVDS) pixel up to 85MHz dot clock for XGA
Clock edge selectable
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDM83R compatible
Block Diagram
P
PLL
TA1 +/-
TB1 +/-
TC1 +/-
TD1 +/-
TCLK1 +/-
(25 to 135MHz)
R/F
/PDWN
1st Link
8
RED1
GREEN1
BLUE1
HSYNC
VSYNC
DE
RED2
GREEN2
BLUE2
TRANSMITTER CLOCK IN
(25 to 85MHz)
1st DATA
2nd DATA
CMOS/TTL INPUT
P
TA2 +/-
TB2 +/-
TC2 +/-
TD2 +/-
TCLK2 +/-
(25 to 85MHz)
M
8
8
8
8
8
8
8
8
2nd Link
LVDS OUTPUT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THC63LVD824A | 制造商:THine Electronics Inc 功能描述: |
| THC63LVD827 | 制造商:THine Electronics Inc 功能描述:Bulk |
| THC63LVDF64B | 制造商:THINE 制造商全稱:THINE 功能描述:LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER |
| THC63LVDF84B | 制造商:THine Electronics Inc 功能描述: |
| THC63LVDM63R | 制造商:THINE 制造商全稱:THINE 功能描述:REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE |
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