參數(shù)資料
型號: TH7120
廠商: Electronic Theatre Controls, Inc.
英文描述: 300 to 930MHz FSK/FM/ASK Transceiver
中文描述: 300至930MHz FSK信號/調頻/調幅器
文件頁數(shù): 10/28頁
文件大?。?/td> 718K
代理商: TH7120
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120
Rev. 005
Page 10 of 28
Data Sheet
Jan. 2002
Programmable Channel Operation
Serial Control Interface Description
A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in multi-
channel mode (see Fig. 2). At each rising edge of the SCLK signal, the logic value on the SDTA pin is written
into a 24-bit shift register. The data stored in the shift register are loaded into one of the 4 appropriate latches
on the rising edge of SDEN. The control words are 24 bits lengths: 2 address bits and 22 data bits. The first
two bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least significant
24 bits are serial-clocked into the shift register. The first incoming bit is the most significant bit (MSB). To
program the transceiver in multi-channel application, four 24-bit words may be sent: A-word, B-word, C-word
and D-word. If individual bits within a word have to be changed, then it is sufficient to program only the appro-
priate 24-bit word. The serial data input timing and the structure of the control words are illustrated in Fig. 2
and 3. Table REGISTER SETTINGS describes the function of each bit.
Figure 2: SCI block diagram
Due to the static CMOS design, the SCI consumes virtually no current and it can be programmed in active as
well as in standby mode.
Figure 3: Serial data input timing
t
EH
t
EW
t
ES
t
CWH
t
CWL
t
CH
t
CS
bit 22
bit 1
bit 0
bit 23
data
Invalid
LSB
MSB
SDTA
SCLK
SDEN
data
Invalid
A - LATCH
ADDR DECODER
B - LATCH
C - LATCH
D - LATCH
22
A-word
22
22
00
01
10
11
2
22
22
22
22
B-word
22
D-word
22
C-word
24-BIT
SHIFT REGISTER
SDEN
SDTA
SCLK
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