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參數(shù)資料
| 型號(hào)： | TEA6422D |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | BUS-CONTROLLED AUDIO MATRIX |
| 中文描述： | 總線控音頻矩陣 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | TEA6422D |
TEA6422
4/10
1
Figure 2.
I2C Bus Timing
I
2
C BUS CHARACTERISTICS
Symbol
Parameter
Test
Conditions
Min.
Max.
Unit
SCL
V
IL
V
IH
I
LI
f
SCL
t
R
t
F
C
I
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Clock Frequency
Input Rise Time
Input Fall Time
Input Capacitance
V
I
= 0 to V
CC
1.5V to 3V
3V to 1.5V
- 0.3
3.0
- 10
0
+ 1.5
V
CC
+ 0.5
+ 10
100
1000
300
10
V
V
μA
kHz
ns
ns
pF
SDA
V
IL
V
IH
I
LI
C
I
t
R
t
F
V
OL
t
F
C
L
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Input Capacitance
Input Rise Time
Input Fall Time
Low Level Output Voltage
Output Fall Time
Load Capacitance
V
I
= 0 to V
CC
1.5V to 3V
3V to 1.5V
I
OL
= 3mA
3V to 1.5V
- 0.3
3.0
- 10
+ 1.5
V
CC
+ 0.5
+ 10
10
1000
300
0.4
250
400
V
V
μA
pF
ns
ns
V
ns
pF
TIMING
t
LOW
t
HIGH
t
SU
, DAT
t
HD
, DAT
t
SU
, STO
t
BUF
t
HD
, STA
Clock Low Period
Clock High Period
Data Set-up Time
Data Hold Time
Set-up Time from Clock High to Stop
Start Set-up Time following a Stop
Start Hold Time
Start Set-up Time following Clock Low-to High
Transition
4.7
4.0
250
0
4.0
4.7
4.0
μs
μs
ns
ns
μs
μs
μs
340
t
SU
, STA
4.7
μs
(start, stop)
t
BUF
t
LOW
t
HIGH
t
f
t
r
t
HD,STA
t
HD,DAT
t
SU,DAT
t
SU,STA
t
SU,STO
SDA
SCL
SDA
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