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參數(shù)資料
| 型號(hào)： | TDF8704 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit high-speed analog-to-digital converter |
| 中文描述： | 8位高速模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | TDF8704 |
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June 1994
9
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must be less than 1 ns.
Full-scale sine wave (f
i
= 4.43 MHz; f
clk
= 50 MHz).
Determined by beat frequency method on a reconstructed sine wave signal for no missing codes and no glitches.
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 4K acquisition points per period. The
calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB
×
6.02 + 1.76 dB.
Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
Measurement taken using video analyser VM700A.
Output data acquisition: the output data is available after the maximum delay time of t
d
.
2.
3.
4.
5.
6.
7.
8.
Timing (note 8; see Figs 5 and 7; f
clk
= 50 MHz)
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
5
12
2
15
ns
ns
ns
3-state output delay times (see Figs 6 and 7)
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
6
12
50
10
10
16
54
14
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.3
Influence of T
amb
on V
I(T)
and V
I(B)
under
5 V supply.
handbook, halfpage
60
3.43
3.45
3.47
MBD868
1.29
1.23
1.25
1.27
VI (T)
(V)
VI (B)
(V)
20
20
60
100
Tamb
o
0.1 mV/K
0.05 mV/K
VI (T)
VI (B)
Fig.4
Influence of supply voltage on V
I(T)
and
V
I(B)
under T
amb
= 25
°
C.
andbook, halfpage
4.25
4.75
5.75
3.38
3.40
3.42
MSA689
5.25
1.28
1.22
1.24
1.26
VI (T)
(V)
VI (B)
(V)
17 mV/V
7 mV/V
VCC
VI (T)
VI (B)
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