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參數(shù)資料
| 型號(hào)： | TDA9870A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Digital TV Sound Processor DTVSP |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| 封裝： | SHRINK, PLASTIC, DIP |
| 文件頁數(shù)： | 79/88頁 |
| 文件大?。?/td> | 362K |
| 代理商： | TDA9870A |
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1998 Aug 10
79
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9870A
As the transfer of coefficients cannot be accomplished
within one audio sample period, it is necessary that
received coefficients be buffered and made active all at the
same time to avoid audio signal transients. The receive
buffer is designed to store up to 8 coefficients in addition
to the CRAM address. Each byte that fits into the buffer is
acknowledged with ACK (acknowledge). If an attempt is
made to write more coefficients than the buffer can store,
the device acknowledges with NACK (not acknowledge)
and any further coefficients are ignored. Coefficients that
are already in the receive buffer remain intact.
An expert mode transfer ends when the I
2
C-bus STOP
condition or a repeated START condition has been
detected. Only those coefficients that have been received
during the last transmission will then be copied from the
buffer to the CRAM.
To make efficient and correct use of the expert mode, it is
recommended to transfer all coefficients for any one
function in a single transmission.
There is no checking of memory addresses and the
automatic incrementing of addresses does not stop at the
highest used CRAM address. The user of this expert mode
must be fully acquainted with the relevant procedures.
More information concerning the functions of this device,
such as the number of coefficients per function, their
default values, memory addresses, etc., can be supplied
on request at a later date.
11 I
2
S-BUS DESCRIPTION
The feature interface of the TDA9870A contains two serial
audio inputs and outputs and associated clock signals.
It can be used to supply, for example, audio signals from
received TV programs to a digital audio output device
(AES/EBU format), or import serial audio signals from
other sources for reproduction through the TV set’s
loudspeaker and/or headphone channels. Apart from such
simple data input or output, it is also possible to run audio
signals through an external DSP, which performs some
additional functions, such as room simulation, Dolby
Surround Pro Logic etc. and feed those signals back into
the loudspeaker and/or headphone channels of the
TDA9870A.
Two serial audio formats are supported at the feature
interface, i.e. the I
2
S-bus format and a very similar
MSB-aligned format. The difference is illustrated in Fig.7.
In both formats the left audio channel of a stereo sample
pair is output first and is placed on the serial data line (SDI
for input, SDO for output) when the word select line (WS)
is LOW. Data is written at the trailing edge of SCK and
read at the leading edge of SCK. The most significant bit
is sent first.
At power-up, the outputs of the feature interface are
3-stated to reduce EMC and allow for combinations with
other ICs. If output is desired, it has to be activated by
means of an I
2
C-bus command.
When the output is enabled, the serial audio data can be
taken from pins SDO1 and SDO2. Depending on the signal
source, switch and matrix positions, the output can be
either mono, stereo or dual language sound on either
output.
The word select output is clocked with the audio sample
frequency at 32 kHz. The serial clock output (SCK) is
clocked at a frequency of 2.048 MHz. This means, that
there are 64 clock pulses per pair of stereo output
samples, or 32 clock pulses per sample. Depending again
on the signal source, the number of significant bits on the
serial data outputs, SDO1 and SDO2, is between
14 and 18.
Apart from just feeding a digital audio device, such as a
DAC or an AES/EBU transmitter, the serial data outputs
can be connected directly to the serial inputs (loop-back
connection) or first to an external device, e.g. a feature
DSP such as the SAA7710 and then back to the serial
inputs. In all of these configurations, the SCK and WS
clocks will be generated by the TDA9870A, which then is
the I
2
S-bus master.
The serial data inputs, SDI1 and SDI2, are active at all
times, independent of the serial data outputs being on or
off. When the serial data outputs are off (either after
power-up or via the appropriate I
2
C-bus command) serial
data and clocks WS and SCK from a separate digital audio
source can be fed into the TDA9870A, be processed and
output in accordance with internal selector positions,
provided that the following criteria are met:
32 kHz audio sample frequency
32 clock bits per sample
External timing and data synchronized to TDA9870A.
In such cases, the external source is the I
2
S-bus master
and the TDA9870A is the I
2
S-bus slave.
To support synchronization of external devices or as a
master clock for them, a system clock output, SYSCLK, is
available from the TDA9870A. At power-up it is off. It can
be enabled and the output frequency set via an I
2
C-bus
command. Available output frequencies are
8.192, 12.288, 16.384 and 24.576 MHz.
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