參數(shù)資料
型號: TDA9855WP
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: I2C-bus controlled BTSC stereo/SAP decoder and audio processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC68
文件頁數(shù): 18/52頁
文件大小: 345K
代理商: TDA9855WP
1997 Nov 04
18
Philips Semiconductors
Product specification
I
2
C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9855
A
UTOMATIC
V
OLUME
L
EVEL CONTROL
(AVL)
Z
i
V
i(rms)
input impedance
maximum input voltage
(RMS value)
gain, maximum boost
maximum attenuation
equivalent step width between
the input stages
(soft switching system)
input level at maximum boost
(RMS value)
input level at maximum
attenuation (RMS value)
output level in AVL operation
(RMS value)
DC offset between different
gain steps
8.8
2
11.0
13.2
k
V
THD < 0.2%
G
v
5
14
6
15
1.5
7
16
dB
dB
dB
G
step
V
i(rms)
see Fig.4
0.1
V
see Fig.4
1.125
V
V
o(rms)
see Fig.4
160
200
250
mV
V
DC(OFF)
voltage at pin C
AV
6.50 to 6.33 V or
6.33 to 6.11 V or
6.11 to 5.33 V or
5.33 to 2.60 V; note 6
AT1 = 0; AT2 = 0; note 7
AT1 = 1; AT2 = 0; note 7
AT1 = 0; AT2 = 1; note 7
AT1 = 1; AT2 = 1; note 7
normal mode; CCD = 0; note 8 1.6
6
mV
R
att
discharge resistors for attack
time constant
340
590
0.96
1.7
420
730
1.2
2.1
2.0
520
910
1.5
2.6
2.4
k
k
μ
A
I
dec
E
FFECT CONTROLS
α
spat1
α
spat2
charge current for decay time
anti-phase crosstalk by spatial
effect
52
30
%
%
phase shift by pseudo-stereo
see Fig.5
V
OLUME TONE CONTROL PART
(
INPUT PINS
VIL
AND
VIR
TO PINS
OUTX
AND
OUTS)
Z
i
Z
o
R
L
C
L
V
i(rms)
volume input impedance
output impedance
output load resistance (AC)
output load capacitance
maximum input voltage
(RMS value)
noise output voltage
8.0
5
2.0
10.0
80
2.15
12.0
120
2.5
k
k
nF
V
THD < 0.5%
V
no
CCIR 468-2 weighted;
quasi peak
G
c
= 16 dB
G
c
= 0 dB
mute position
110
33
10
220
50
μ
V
μ
V
μ
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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