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參數(shù)資料
| 型號(hào)： | TDA9847T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | TV and VTR stereo/dual sound processor with digital identification |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 147K |
| 代理商： | TDA9847T |
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1995 May 23
13
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
Notes to the characteristics
1.
V
o
= 0.5 V (RMS value); f = 1 kHz.
2.
Without de-emphasis capacitors with respect to nominal gain.
3.
In dual mode: A (B)-signal into B (A) channel; in stereo mode: R-signal into left channel; L-signal = 0.
4.
Tuner input signal, measured with PCALH reference front end (
1
2
EMF, 75
, 2T/20T/white bar, 100% video) and
PC/SC
1
= 13 dB; PC/SC
2
= 20 dB. The pilot band-pass has to be aligned.
5.
Bandwidth of the pilot BP-filter B
3 dB
= 1.2 kHz. V
i2
input driven with identification-modulated pilot carrier and white
noise.
6.
Identification window is defined as twice the pull-in frequency range (lower plus upper side) of identification PLL
(steady detection) plus window increase due to integrator (fluctuating detection).
7.
The maximal total system identification time on is equal to t
ident(on)
plus t
acqui AGC
.
8.
The maximal total system identification time off is equal to t
ident(off)
.
t
ident(on)
total identification time on
stereo; note 7
dual; note 7
stereo; note 8
dual; note 8
0.35
0.35
0.60
0.60
2.0
2.0
1.5
1.5
s
s
s
s
t
ident(off)
total identification time off
LED (pins 18 and 19)
V
L(off)
V
L(on)
I
L(off)
I
L(on)
output voltage
output voltage
input current
input current
LED off
LED on
LED off
LED on
8.8
0.7
1
12
V
V
μ
A
mA
Control input ports C1 to C3 (pins 1, 2 and 24)
V
IL
V
IH
I
IL
I
IH
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
2.0
5.0
0.8
8.8
-1
1
V
V
μ
A
μ
A
Control input Port C4 (pin 3)
V
IL
V
CT
V
IH
I
IL
I
CT
I
IH
t
h1
t
h2
t
su1
t
su2
LOW level input voltage
3-state level input voltage
HIGH level input voltage
LOW level input current
3-state level input current
HIGH level input current
HIGH level hold time
LOW level hold time
HIGH level set-up time
LOW level set-up time
0
1.5
2.8
5
5
0.25
0.25
1.8
5.0
0.8
2.1
8.8
1
1
1
V
V
V
μ
A
μ
A
μ
A
μ
s
μ
s
μ
s
μ
s
see Fig.5
see Fig.5
see Fig.5
see Fig.5
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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