參數(shù)資料
型號(hào)： TDA9332H
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： I2C-bus controlled TV display processors
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 23/56頁(yè)
文件大?。?/td> 228K
代理商： TDA9332H
2000 May 08
23
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
Horizontal synchronization and deflection
H
D
INPUT SIGNAL
;
PIN
24
V
IL
V
IH
I
i(HD)
t
r(HD)
t
f(HD)
t
W(HD)
I
NTERNAL REFERENCE SIGNAL
;
CRYSTAL OR RESONATOR CONNECTED TO PINS
20
AND
21; note 28
LOW-level of input voltage
HIGH-level of input voltage
input current
rise time
fall time
pulse width
note 27
note 27
2.0
10
200 ns
0.8
5.5
+10
100
100
1/4 line
V
V
μ
A
ns
ns
f
xtal
R
s(xtal)
V
i(stab)(p-p)
resonator frequency
resonator series resistance
stabilized input signal
(peak-to-peak value)
maximum transconductance
input impedance
input capacitance
output capacitance
0.5
12
0.8
30
1.0
MHz
V
C
L
= 60 pF
g
m(max)
Z
i
C
i
C
o
E
XTERNAL REFERENCE SIGNAL
;
INPUT PIN
20
4
50
5
10
5
mA/V
k
pF
pF
f
XTALI
V
i(XTALI)(p-p)
input signal frequency
input signal amplitude
(peak-to-peak value)
0.8
12
2
MHz
V
AC coupled
F
IRST CONTROL LOOP
; note 29
f
o(nom)
free-running frequency
1f
H
mode; note 30
2f
H
mode; note 30
2f
H
mode; HDTV = 1;
note 30
note 30
15.65
31.3
33.7
kHz
kHz
kHz
f
nom
tolerance on free-running
frequency
holding/catching range of PLL
±
1
%
f
h/cr
1f
H
mode
2f
H
mode
1f
H
mode
2f
H
mode
1f
H
mode
2f
H
mode
±
0.75
±
1.5
2
1
15
30
±
0.8
±
1.6
±
0.85
±
1.7
+2
+1
25
50
100
kHz
kHz
μ
s
μ
s
kHz
kHz
kHz/s
t
line
maximum line time difference per
line
f
contr
frequency control range in
multi-sync mode
f
corr
maximum speed of frequency
correction in multi-sync mode
voltage on pin HSEL
V
HSEL
1f
H
mode
2f
H
mode; pin must be left
open circuit
0
4
5
1
5.5
V
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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