參數(shù)資料
型號(hào): TDA9321
廠商: NXP Semiconductors N.V.
英文描述: I2C-bus controlled TV input processor
中文描述: 的I2C控制的電視處理器總線輸入
文件頁(yè)數(shù): 19/44頁(yè)
文件大?。?/td> 249K
代理商: TDA9321
1998 Dec 16
19
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV input processor
TDA9321H
I
source(max)
B
v(
3dB)
maximum source current
3 dB bandwidth of
demodulated output signal
differential gain
differential phase
video non-linearity
white spot clamping level
noise inverter clamping level
noise inverter insertion level
(identical to black level)
intermodulation at ‘blue’
6
8
5
10
mA
MHz
G
dif
dif
NL
vid
V
clamp
N
clamp
N
ins
note 9
notes 6 and 9
note 10
2.5
6.0
1.5
2.7
1.5
2.5
5
%
deg
%
V
V
V
note 11
note 11
d
blue
notes 6 and 12
f = 0.92 or 1.1 MHz
f = 2.66 or 3.3 MHz
notes 6 and 12
f = 0.92 or 1.1 MHz
f = 2.66 or 3.3 MHz
notes 6 and 13
60
60
66
66
dB
dB
d
yellow
intermodulation at ‘yellow’
56
60
56
49
62
66
60
53
5.5
2.5
65
dB
dB
dB
dB
mV
mV
S/N
W
S/N
UW
V
rc
V
rc(2H)
weighted signal-to-noise ratio
unweighted signal-to-noise ratio notes 6 and 13
residual carrier signal
2nd harmonic of residual carrier
signal
power supply ripple rejection
note 6
note 6
PSRR
at the output
40
dB
VIF
AND TUNER
AGC; note 14
Timing of VIF-AGC with a 2.2
μ
F capacitor (pin DEC
VIF
)
MVI
modulated video interference
60% AM for 1 to 100 mV;
0 to 200 Hz; system B/G
VIF input signal
amplitude increase of
52 dB; positive and
negative modulation
VIF input signal
amplitude decrease of
52 dB
negative modulation
positive modulation
negative modulation
positive modulation
capacitor on pin 4 is
0.5
μ
F
10
%
t
res
response time
2
ms
50
100
10
200
2
ms
ms
μ
A
nA
%
I
L
leakage current of the capacitor
on pin 4
V
o(v)
change in video output signal
amplitude over 1 vertical period
for peak white AGC at positive
modulation
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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