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參數(shù)資料
| 型號： | TDA9210 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大小： | 2124K |
| 代理商： | TDA9210 |
TDA9210
12/19
11 - I2C REGISTER DESCRIPTION
Table 1. Register Sub-addressed - I2C Table 1
Note 2: For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed.
Note 3: For Cut Off Output DC Level, codes below 40 (dec) are not allowed
Note 4: To be set to 0 (dec) for application with tR/tF >5.5ns
Table 2. BPCP & OCL Register (R8) - I2C Table 2 (see also Figure 8)
Sub-address
Register Names
POR Value Max. Value
Hex
Dec
Hex
Dec
Hex
Dec
01
Contrast (CRT) - Note 2
8-bit DAC
B4
180
FE
254
02
Brightness (BRT)
8-bit DAC
B4
180
FF
255
03
Drive 1 (DRV) - Note 2
8-bit DAC
B4
180
FE
254
04
Drive 2 (DRV) - Note 2
8-bit DAC
B4
180
FE
254
05
Drive 3 (DRV) - Note 2
8-bit DAC
B4
180
FE
254
06
Not Used
-
07
OSD Contrast (OSD)
4-bit DAC
09
0F
15
08
BPCP & OCL
Refer to the I2C table 2
04
09
Miscellaneous
Refer to the I2C table 3
1C
28
0A
10
Cut Off Out 1 DC Level (Cut-off) - Note 3
8-bit DAC
B4
180
FF
255
0B
11
Cut Off Out 2 DC Level (Cut-off) - Note 3
8-bit DAC
B4
180
FF
255
0C
12
Cut Off Out 3 DC Level (Cut-off) - Note 3
8-bit DAC
B4
180
FF
255
0D
13
Bandwidth Adjustment (BW) - Note 4
4-bit DAC
07
0F
15
b7
b6
b5
b4
b3
b2
b1
b0
Function
POR Value
0
Internal BPCP triggered by HSYNC
x
0
1
Internal BPCP triggered by BLK
0
Internal BPCP synchronized by the trailing edge
x
0
1
Internal BPCP synchronized by the leading edge
0
Internal BPCP Width = 0.33 s
0
1
Internal BPCP Width = 0.66 s
x
0
1
0
Internal BPCP Width = 1 s
0
1
Internal BPCP Width = 1.33 s
1
Internal BPCP = BPCP input
0
Normal Operation
x
1
Reserved (Force BPCP to 1 in test)
0
Normal Operation
x
1
Reserved (Force OCL to 1 in test)
0
Internal OCL pulse triggered by BLK
x
1
Internal OCL pulse = Internal BPCP
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