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參數(shù)資料
| 型號(hào)： | TDA9210 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS |
| 中文描述： | 150 MHz像素的顯示器視頻控制器 |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大小： | 206K |
| 代理商： | TDA9210 |
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TDA9210
12/19
11 - I
2
C REGISTER DESCRIPTION
Register Sub-addressed - I
2
C Table 1
For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed.
For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed (Register 06).
For Cut Off Output DC Level, output voltage is linear between code 10 and code 235 (Registers 0A, 0B, 0C).
BPCP & OCL Register (R8) - I
2
C Table 2 (see also Figure 8)
Sub-address
Register Names
POR Value
Max.
Value
Hex
FE
FF
FE
FE
FE
-
0F
Hex
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
Dec
01
02
03
04
05
06
07
08
09
10
11
12
13
Hex
B4
B4
B4
B4
B4
-
09
04
1C
B4
B4
B4
07
Dec
180
180
180
180
180
-
09
04
28
180
180
180
07
Dec
254
255
254
254
254
-
15
Contrast (CRT)
Brightness (BRT)
Drive 1 (DRV)
Drive 2 (DRV)
Drive 3 (DRV)
Not Used
OSD Contrast (OSD)
BPCP & OCL
Miscellaneous
Cut Off Out 1 DC Level (Cut-off)
Cut Off Out 2 DC Level (Cut-off)
Cut Off Out 3 DC Level (Cut-off)
Bandwidth Adjustment (BW)
8-bit DAC
8-bit DAC
8-bit DAC
8-bit DAC
8-bit DAC
4-bit DAC
Refer to the I
2
C table 2
Refer to the I
2
C table 3
8-bit DAC
8-bit DAC
8-bit DAC
4-bit DAC
FF
FF
FF
0F
255
255
255
15
b7
b6
b5
b4
0
0
0
0
0
0
0
0
1
b3
b2
b1
b0
0
1
Function
POR Value
x
Internal BPCP triggered by HSYNC
Internal BPCP triggered by BLK
Internal BPCP synchronized by the trailing edge
Internal BPCP synchronized by the leading edge
Internal BPCP Width = 0.33
μ
s
Internal BPCP Width = 0.66
μ
s
Internal BPCP Width = 1
μ
s
Internal BPCP Width = 1.33
μ
s
Internal BPCP = BPCP input (Pin 23)
Normal Operation
Reserved (Force BPCP to 1 in test)
Normal Operation
Reserved (Force OCL to 1 in test)
Internal OCL pulse triggered by BLK (pin 24)
Internal OCL pulse = Internal BPCP
0
1
x
0
0
1
1
0
1
0
1
x
0
1
x
0
1
x
0
1
x
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