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BLK
HSYNC
BPCP
Internal pulse width is controlled by I
2
C
9
Figure 1
FUNCTIONAL DESCRIPTION
Input Stage
The R, G and B signals must be fed to the three
inputsthroughcouplingcapacitors(100nF).
Themaximuminput peak-to-peakvideo amplitude
is 1V.
The inputstage includes a clamping function.This
clamp is using the input serial capacitor as ”mem-
ory capacitor” and is gatedby an internally gener-
ated”Back-Porch-Clamping-Pulse(BPCP)”.
The synchronizationedge of the BPCPis selected
accordingbit 0 of registerR8.
When B0R8 is set to 1, the BPCPis synchronized
ontheleadingedgeoftheblankingpulseBLKinputs
onPin14(seeFigure1).B7R8allowstousepositive
or negativeblanking signal on Pin 14. At power on
resetTDA9203Ause onlypositiveblanking.
WhenB0R8isclearto0, theBPCPis synchronized
onthesecondedgeof thehorizontalpulseHSYNC
inputs on Pin 24. An automatic function allows to
usepositive or negativehorizontalpulseon Pin24
(seeFigure 2).
In both case BPCP width is adjustableby I
2
C, B1
and B2 of registerR8 (see R8 TableP8).
Contrast Adjustment
(8 bits)
The contrast adjustment is made by controlling
simultaneously the gain of three internal variable
gain amplifiers through the I
2
C bus interface.
The contrast adjustment allows to cover a typical
range of 48dB.
ABLControl
The TDA9203A I
2
C preamplifierprovides an ABL
input (automatic beam limitation) to attenuate
R,G,B video signals according to beam intensity.
The operating range is 2.5V typicaly, from 5.3V to
2.8V.Atypical 12dBMax. attenuationis appliedto
the signal whatever the current gain is. Refer to
Figure 3 forABL input attenuationrange.
In case of softwarecontrol,the ABLinput must be
pulled to AV
DD
through a resistor to limit power
consumption(see Figure 11).
ABL input voltage must not exceeed AV
DD
. Input
resistoris 10k
and equivalentschematicgivenin
Figure 11.
HSYNC
BPCP
Internal pulse width is controlledby I
2
C
9
Figure 2
BrightnessAdjustment
(8 bits)
As for the contrast adjustment, the brightness is
controlledby I
2
C.
The brightness function consists to add the same
DC offsetto the threeR,G,B signalsaftercontrast
amplification. This DC-Offset is present only out-
side the blanking pulse (see Figure4).
The DC output level during the blanking pulse, is
forced to ”INFRA-BLACK” level (V
DC
).
DriveAdjustment
(3x 8 bits)
Inordertoadjustthewhitebalance, theTDA9203A
offersthepossibilitytoadjustseparatelythe overall
gain of each complete video channel.The gain of
each channel is controlledby I
2
C (8bits each).
Theverylargedriveadjustmentrange(48dB)allows
differentstandardor customcolor temperature.
It can also be used to adjust the outputvoltagesat
the optimum amplitude to drive the C.R.T drivers,
keepingthewholecontrastcontrolforend-useronly.
The drive adjustment is located after the CON-
TRAST,BRIGHTNESSand OSDswitchblocks,so
that the white balance will remains correct when
BRT is adjusted, and will also be correct on OSD
portionof the signal.
2
0
-2
-4
-6
-8
-10
-12
-14
1
2
3
4
5
6
7
8
9
Attenuation (dB)
V
IN
(V)
9
Figure 3
TDA9203A
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