參數(shù)資料
型號(hào)： TDA8776AK
廠商： NXP SEMICONDUCTORS
元件分類： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 0.002 us SETTLING TIME, 10-BIT DAC, PQCC28
封裝： PLASTIC, SOT-261-2, LCC-28
文件頁(yè)數(shù)： 18/20頁(yè)
文件大小： 120K
代理商： TDA8776AK
1996 Jun 04
7
Philips Semiconductors
Product specication
10-bit, 1000 Msps Digital-to-Analog
Converter (DAC)
TDA8776A
Notes
1. D0 to D9 connected to either HIGH or LOW level, CLK is HIGH and CLK is LOW.
2. The analog output voltages (VOUT and VOUT) are negative with respect to AGND (see Table 1). The external output
resistance between AGND and each of these outputs is typically 50
.
3. Due to on-chip regulator behaviour a warm-up time is necessary to reach optimal performances; a typical time is
1 minute.
4. Devices with higher SFDR (min.) can be delivered on special request.
5. The worst case characteristics are obtained at the transition from input code 0 to 1023 and if an external load
impedance greater than 50
is connected between VOUT or VOUT and AGND in parallel with the external 50 load.
The specified values have been measured directly on a 50
load between VOUT and AGND. No further load
impedance between VOUT and AGND has been applied. All input data is latched at the falling edge of the clock.
6. The data set-up (tSU;DAT) is the minimum period preceding the falling edge of the clock that the input data must be
stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
falling edge of the clock and still be recognized. The data hold time (tHD;DAT) is the minimum period following the
falling edge of the clock that the input data must be stable in order to be correctly registered. A negative hold time
indicates that the data may be released prior to the falling edge of the clock and still be recognized.
7. The definition of glitch energy and the measurement set-up are shown in Fig.10. The glitch energy is measured at
the input transition between code 511 to 512.
Table 1
Input coding and DAC output voltages (typical values; referenced to AGND regardless of the offset voltage)
Switching characteristics (fclk = 1000 MHz); notes 5 and 6; see Figs 8 and 9
tSU;DAT
data set-up time
400
500
ps
tHD;DAT
data hold time
100
150
ps
tPD
propagation delay time
0.8
0.9
ns
tS1
settling time
10% to 90% full scale
0.5
ns
tS2
settling time
change to
±1 LSB
2.0
ns
td
input to 50% output delay time
1.4
1.5
ns
Output transients; glitches (fclk = 1000 MHz); note 7; see Fig.10
Eg
differential glitch energy from code
transition 511 to 512
12pV.s
CODE
BINARY INPUT DATA
DAC OUTPUT
VOLTAGES (V)
ZL =50
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VOUT
0
0000000000
0
1.0
1
0000000001
0.0010
0.9990
.
..........
.
512
1000000000
0.5
.
..........
.
1022
1111111110
0.9990
0.0010
1023
1111111111
1.0
0
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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