參數(shù)資料
型號(hào)： TDA8768BH/8/C3
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, 1.30 MM LEAD LENGTH, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 2/30頁(yè)
文件大?。?/td> 547K
代理商： TDA8768BH/8/C3
Philips Semiconductors
TDA8768B
12-bit, 80 Msps Analog-to-Digital Converter (ADC)
Product data
Rev. 02 — 20 January 2004
10 of 30
9397 750 12338
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
D = guaranteed by design; C = guaranteed by characterization; I = 100% industrially tested.
[2]
The circuit has two clock inputs: CLK and CLK. There are 2 modes of operation:
a) Differential AC driving mode: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of
2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLK input with the same signal, sampling
takes place at the rising edge of the clock signal. It is recommended to decouple the CLK or CLK input to DGND via a 100 nF
capacitor.
b) TTL mode: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In this event pin CLK has to
be connected to ground.
[3]
The ADC input range can be adjusted with an external reference voltage connected to pin Vref. This voltage has to be referenced to
VCCA; see Figure 8.
[4]
The
3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
Effective number of bits[7]
ENOB
effective number of bits
TDA8768BH/5
(fCLK = 52 MHz)
fi = 4.43 MHz
C
-
11.7
-
bits
fi = 10 MHz
C
-
11.7
-
bits
fi = 15 MHz
C
-
11.7
-
bits
fi = 20 MHz
C
-
9.6
-
bits
effective number of bits
TDA8768BH/8
(fCLK = 80 MHz)
fi = 4.43 MHz
C
-
9.8
-
bits
fi = 10 MHz
C
-
9.8
-
bits
fi = 15 MHz
C
-
9.8
-
bits
fi = 20 MHz
I
-
9.6
-
bits
effective number of bits
TDA8768BH/8/S1
(fCLK = 80 MHz)
fi = 4.43 MHz
C
-
10.4
-
bits
fi = 10 MHz
C
-
10.4
-
bits
fi = 15 MHz
C
-
10.4
-
bits
Intermodulation; (fCLK = 55 MHz; fi = 20 MHz)[8]
TTIR
two-tone intermodulation
rejection
fCLK = 80 MHz at 7 dBFS
C
-
62
-
dB
d3
third-order intermodulation
distortion
fCLK = 80 MHz at 7 dBFS
C
-
67
-
dB
Bit error rate (fCLK = 55 MHz)
BER
bit error rate
fi = 20 MHz; VI = ±16 LSB at
code 2047
C-
1014
-
times/
sample
Timing (CL = 10 pF); see Figure 3; [9]
td(s)
sampling delay time
C
-
0.25
1
ns
th
output hold time
C
4
6.4
-
ns
td
output delay time
C
-
9.0
13
ns
3-state output delay times; see Figure 4
tdZH
enable HIGH
C
-
5.1
9.0
ns
tdZL
enable LOW
C
-
7.0
11
ns
tdHZ
disable HIGH
C
-
9.7
14
ns
tdLZ
disable LOW
C
-
9.5
13
ns
Table 6:
Characteristics…continued
VCCA = 4.75 V to 5.25 V (V2 to V44, V3 to V4 and V41 to V40); VCCD = 4.75 V to 5.25 V (V37 to V38 and V15 to V17);
VCCO = 3.0 V to 3.6 V (V33 to V34); AGND and DGND shorted together; Tamb = 40 °Cto+85 °C; Vi(p-p) Vi(p-p) = 1.9 V;
Vref =VCCA3 1.75 V; VI(CM) =VCCA3 1.6 V; typical values measured at VCCA =VCCD =5V, VCCO = 3.3 V, Tamb =25 °C and
CL = 10 pF; unless otherwise specied.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
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