參數(shù)資料
型號(hào)： TDA8768AH/7
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： ADC
英文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 3/32頁(yè)
文件大?。?/td> 1434K
代理商： TDA8768AH/7
Philips Semiconductors
TDA8768A
12-bit, 70 Msps Analog-to-Digital Converter (ADC)
Product data
Rev. 02 — 03 July 2002
11 of 32
9397 750 09656
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
[1]
D = guaranteed by design; C = guaranteed by characterization; I = 100% industrially tested.
[2]
The circuit has two clock inputs: CLK and CLK. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1:1 with VCCD) CLK and CLK inputs are at differential PECL levels.
b) PECL mode 2: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLK or CLK input to DGND via a 100 nF capacitor.
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
In that case CLK pin has to be connected to the ground.
[3]
The ADC input range can be adjusted with an external reference connected to Vref pin. This voltage has to be referenced to VCCA;
[4]
The
3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[5]
Total Harmonic Distortion (THD) is obtained with the addition of the rst ve harmonics:
where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6.
[6]
Signal-to-noise ratio (SNR) takes into account all harmonics above ve and noise up to nyquist frequency; see Figure 8.
[7]
Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up
to half of the clock frequency (Nyquist frequency). Conversion to SINAD is given by SINAD = ENOB
× 6.02 + 1.76 dB; see Figure 5.
[8]
Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter (
6 dB below full scale for each input signal).
d3(IM3) is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.
[9]
Output data acquisition: the output data is available after the maximum delay of td; see Figure 3.
3-state output delay times; see Figure 4
tdZH
enable HIGH
C
-
5.1
9.0
ns
tdZL
enable LOW
C
-
7.0
11
ns
tdHZ
disable HIGH
C
-
9.7
14
ns
tdLZ
disable LOW
C
-
9.5
13
ns
Table 6:
Characteristics…continued
VCCA =V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD =V37 to V38 and V15 to V17 = 4.75 to 5.25 V;
VCCO =V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = 40 to 85 °C; VI(p-p) VI(p-p) = 1.9 V;
Vref =VCCA31.75 V; VI(CM) =VCCA31.6V; typical values measured at VCCA =VCCD = 5 V and VCCO = 3.3 V, Tamb =25 °C
and CL = 10 pF; unless otherwise specied.
Symbol
Parameter
Conditions
Test [1]
Min
Typ
Max
Unit
THD
20 log
2nd
()
2
3rd
()
2
4th
()
2
5th
()
2
6th
()
2
++
+
F
2
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=
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