參數(shù)資料
型號: TDA8767H/3-T
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 12/20頁
文件大小: 103K
代理商: TDA8767H/3-T
1999 Feb 16
2
Philips Semiconductors
Preliminary specication
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
FEATURES
12-bit resolution
Sampling rate up to 30 MHz
3 dB bandwidth of 18 MHz
No missing codes guaranteed
5 V power supplies
Binary or two’s complement CMOS outputs
In-range CMOS output
TTL/CMOS compatible static digital inputs
3 to 5 V CMOS digital outputs
TTL compatible clock input
Power dissipation 335 mW (typ.)
Low analog input capacitance (typ. 2 pF), no buffer
amplifier required
No external sample-and-hold circuit required
Differential or single analog Input
External amplitude range control
Voltage controlled regulator included.
APPLICATIONS
High-speed analog-to-digital conversion for:
– Video signal digitizing
– High Definition TV (HDTV)
– Imaging (camera, scanner)
– Medical imaging
– Telecommunication
– Base-station receiver.
GENERAL DESCRIPTION
The TDA8767 is a bipolar 12-bit Analog-to-Digital
Converter (ADC) for imaging or other applications.
It converts the analog input signal into 12-bit binary coded
digital words at a maximum sampling rate of 30 MHz.
All digital inputs and outputs are CMOS compatible.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
4.75
5.0
5.25
V
VCCD
digital supply voltage
4.75
5.0
5.25
V
VCCO
output supply voltage
3.0
3.3
5.25
V
ICCA
analog supply current
40
tbf
mA
ICCD
digital supply current
22
tbf
mA
ICCO
output supply current
fclk = 4 MHz; fi = 400 kHz
3.2
tbf
mA
ILE
integral non-linearity
fclk = 4 MHz; fi = 400 kHz
±3.0
±4.0
LSB
DLE
differential non-linearity
fclk = 4 MHz; fi = 400 kHz;
no missing codes
±0.6
±1
LSB
fclk(max)
maximum clock frequency
TDA8767H/1
10
MHz
TDA8767H/2
20
MHz
TDA8767H/3
30
MHz
Ptot
total power dissipation
335
mW
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