參數(shù)資料
型號: TDA8757AHL/21
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝: PLASTIC, HLQFP-144
文件頁數(shù): 13/37頁
文件大?。?/td> 908K
代理商: TDA8757AHL/21
Philips Semiconductors
TDA8757A
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 22 March 2002
20 of 37
9397 750 09549
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
9.1.5
VCO register
Bits ‘Z2’, ‘Z1’ and ‘Z0’ enable the internal resistance for the VCO lter to be selected.
Bits ‘Vco1’ and ‘Vco0’ control the VCO gain.
The default programmed value is as follows:
Internal resistance = 2.25 k
VCO gain = 70 MHz/V.
9.1.6
Divider register
This register controls the PLL frequency. Bits ‘Di8’ to ‘Di0’ are the LSB bits. The
default programmed value is 0110 1001 1000 = 1688.
The MSB bits (‘Di11’, ‘Di10’ and ‘Di9’) and the LSB bit ‘Di0’ have to be programmed
before bits ‘Di8’ to ‘Di1’ in order to have the required divider ratio. Bit ‘Di0’ is used for
the parity divider number (Di0 = 0: even number; Di0 = 1: odd number). It should be
noted that if the I2C-bus programming is done in mode 1 and the bit ‘Di0’ has to be
toggled, then the registers have to be loaded twice to have the update divider ratio.
9.1.7
Phase register
Bit ‘Ckext’ is logic 0 when the used clock is the PLL clock and logic 1 when the used
clock is the external clock.
Bit ‘Ckrs’ is logic 1 when the synchronization is done with CKREF (see Figure 3).
Bits ‘P4’ to ‘P0’ are used to program the phase shift for clock CKDATA.
Table 9:
VCO register bits
Z2
Z1
Z0
Resistance (k
)
0
high-impedance
0019
0106.4
0114.5
1003.2
1
0
1
2.25
1101.6
1111.1
Table 10: VCO gain control
Vco1
Vco0
VCO gain (MHz/V)
Pixel clock
frequency range
(MHz)
0
20
12 to 28
0
1
30
28 to 55
1
0
60
55 to 115
1
115
115 to 205
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