參數(shù)資料
型號： TDA8754HL/17/C1
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù)： 25/57頁
文件大?。?/td> 259K
代理商： TDA8754HL/17/C1
TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
31 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.11 Coast register
Remark: When POSTCOAST[4:0] = PRECOAST[2:0] = 0, then the coast pulse equals
the VSYNC input.
9.12 Horizontal sync selection register
Table 41.
COAST - coast register (address 12h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
PRE
COAST2
PRE
COAST1
PRE
COAST0
POST
COAST4
POST
COAST3
POST
COAST2
POST
COAST1
POST
COAST0
Reset
00000000
Access
WWWWWWWW
Table 42.
COAST - coast register (address 12h) bit description
Bit
Symbol
Description
7 to 5 PRECOAST[2:0]
programs the length (in numbers of pixel clocks) of the coast pulse before the edge of the
vertical sync signal
4 to 0 POSTCOAST[4:0] programs the length (in numbers of pixel clocks) of the coast pulse after the edge of the vertical
sync signal
Table 43.
HSYNCSEL - horizontal sync selection register (address 13h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
----
TESTCNT
BYSEPA
HSSEL
HSS
Reset
XXXX
0100
Access
WWWWWWWW
Table 44.
HSYNCSEL - horizontal sync selection register (address 13h) bit description
Bit
Symbol
Description
7 to 4
-
not used
3
TESTCNT
this bit is used to test the pixel counter
0 = normal mode
1 = test mode
2
BYSEPA
enables the sync separator for the PLL reference to be bypassed
0 = Hsync from the separator
1 = bypass of the sync separator
1
HSSEL
enables either the HSYNC or CHSYNC input signal to be selected
0 = HSYNC input
1 = CHSYNC input
0
HSS
enables either the HSYNC or CHSYNC input signal to be inverted
0 = non-inverted
1 = inverted
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