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參數(shù)資料
| 型號(hào)： | TDA8046H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Multi-mode QAM demodulator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大?。?/td> | 245K |
| 代理商： | TDA8046H |
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1996 Nov 19
12
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
Fig.8 DFE equalizer structure.
handbook, full pagewidth
MGG170
FEED
FORWARD
EQUALIZER
TAPS CALCULATION
DECISION
FEEDBACK
EQUALIZER
TAPS CALCULATION
input
output
decision
+
7.1.3
L
OCK DETECTOR
The lock detector indicates whether all algorithms in the
demodulator are converged or not. For a symbol error rate
(at the input of the demodulator) smaller than 2
×
10
2
, the
detector will give the indication ‘LOCK’ (I
2
C-bus bit
LK = 1). For larger symbol error rates, the detector will
generate the ‘UNLOCK’ signal (I
2
C-bus bit LK = 0).
It should ne noted that this ‘UNLOCK’ signal is generated
before any other part of the demodulator loses lock.
The lock detector is part of the carrier recovery loop, see
Fig.9. The Lock Detector Threshold (LDT) can be changed
with the help of the I
2
C-bus. The estimation algorithm used
in the lock detector also provides information about the
SER ratio which can be read out via the I
2
C-bus interface.
For characteristics see Chapter 11.
7.1.4
C
ARRIER RECOVERY
The carrier recovery detector consists of a
Phase-Frequency Detector (PFD) and Phase Detector
(PD). Depending on the mode of operation, the carrier
recovery is switched either between the phase frequency
(no lock) or the phase detector (lock). The carrier recovery
consists of the following two loops:
1.
The outer loop; this loop controls the phase and
frequency of the incoming QAM signal at the IF
frequency in such a way that the constellation is
optimally positioned for detection.
The inner loop; the bandwidth of this loop can be large
and can therefore reduce the influence of large
bandwidth phase noise.
2.
A fully digital carrier recovery function is also possible and
can be selected via the I
2
C-bus. Should this configuration
be used, then the external components of the loop filter will
not have to be implemented.
Four different maximum DAC output currents can be
selected via the I
2
C-bus. The output currents of the DAC
are defined in such a way that a VCO with a behaviour as
shown in Fig.9 can be connected directly to the output of
the integrated operational amplifier. Should the VCO slope
be negative then the sign of the current can be inverted by
the I
2
C-bus. Figure 10 defines the DAC output currents.
For characteristics see Chapter 12.
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