參數(shù)資料
型號: TDA7535
廠商: 意法半導體
英文描述: DELTA/SIGMA CASCADE 20 BIT STEREO DAC
中文描述: 三角洲/西格瑪級聯(lián)20位立體聲DAC
文件頁數(shù): 5/9頁
文件大?。?/td> 160K
代理商: TDA7535
5/9
TDA7535
Figure 2. I
2
S Timings
(1)
SCK clock defines the Fs, being the Sample Rate. This input clock needs a jitter below ~212ps
RMS
(2)
FSYNC switches inside the time window as specified w.r.t. to falling edge of SCK
Figure 3. Power Up & Reset Sequence
I
2
S bit clock (SCK) must be present 20ms before reset release to allow PLL locking.
Timing
Description
Minimum
Maximum
Unit
t
sck
Clock Cycle
(1)
1/(64*Fs) -
150ps
RMS
1/(64*Fs) +
150ps
RMS
ns
t
sckpl
SCK Phase Low
0.5*t
sck
- 1%
0.5*t
sck
+1%
ns
t
sckph
SCK Phase High
0.5*t
sck
- 1%
0.5*t
sck
+1%
ns
t
lrw-
FSYNC switching time window before SCK falling edge
(2)
0
0.125*t
sck
-10
ns
t
lrw+
FSYNC switching time window after SCK falling edge
(2)
0
0.125*t
sck
-10
ns
t
sds
SDATA setup time
60
ns
t
sdh
SDATA hold time
30
ns
t
sckr
SCK rise time
1.5
ns
t
sckf
SCK fall time
1.5
ns
t
sck
t
sckpl
t
sds
t
lrw-
t
sckph
t
lrw+
t
sdh
Valid
FSYNC
SDATA
SCK
Valid
t
sckf
t
sckr
T
RES
T
RES
Min 50ms
V
DD
RESET
D02AU1418
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相關代理商/技術參數(shù)
參數(shù)描述
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