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參數(shù)資料
| 型號： | TDA7512 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | AM/FM CAR RADIO TUNER IC WITH INTELLIGENT SELECTIVITY SYSTEM ISS |
| 中文描述： | 調(diào)幅/調(diào)頻收音機調(diào)諧器集成電路汽車智能識別系統(tǒng)與國際空間站 |
| 文件頁數(shù)： | 17/42頁 |
| 文件大?。?/td> | 761K |
| 代理商： | TDA7512 |
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TDA7512
1.7
PLL and IF Counter Section
1.7.1
This part contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is required
to build a complete PLL system for FM world tuning and AM upconversion. For auto search stop operation an
IF counter system is available.
The counter works in a two stages configuration. The first stage is a swallow counter with a two modulus (32/33)
precounter. The second stage is an 11-bit programmable counter.
The circuit receives the scaling factors for the programmable counters and the values of the reference frequen-
cies via an I
2
C-Bus interface.The reference frequency is generated by an adjustable internal (XTAL) oscillator
followed by the reference divider. The main reference and step-frequencies are free selectable (RC, PC).
Output signals of the phase detector are switching the programmable current sources. The loop filter integrates
their currents to a DC voltage.
The values of the current sources are programmable by 6 bits also received via the I
2
C Bus (A, B, CURRH, LPF).
To minimize the noise induced by the digital part of the system, a special guard configuration is implemented.
The loop gain can be set for different conditions by setting the current values of the chargepump generator.
PLL Frequency Synthesizer Block
1.7.2
The RF signals applies a two modulus counter (32/33) pre-scaler, which is controlled by a 5-bit A-divider. The
5-bit register (PC0 to PC4) controls this divider. In parallel the output of the prescaler connects to an 11-bit B-
divider. The 11-bit PC register (PC5 to PC15) controls this divider
Dividing range:
f
VCO
= [33 x A + (B + 1 - A) x 32] x f
REF
f
VCO
= (32 x B + A + 32) x f
REF
Important: For correct operation: A
≤
32; B
≥
A
Frequency Generation for Phase Comparison
1.7.3
The phase comparator generates a phase error signal according to phase difference between f
SYN
and f
REF
.
This phase error signal drives the charge pump current generator.
Three State Phase Comparator
1.7.4
This system generators signed pulses of current. The phase error signal decides the duration and polarity of
those pulses. The current absolute values are programmable by A register for high current and B register for
low current.
Charge Pump Current Generator
1.7.5
Switching the chargepump in low current mode can be done either via software or automatically by the inlock
detector, by setting bit LDENA to "1".
After reaching a phase difference about lower than 40nsec the chargepump is forced in low current mode. A
new PLL divider alternation by I
2
C-Bus will switch the chargepump in the high current mode.
Inlock Detector
1.7.6
An internal voltage divider at pin VREF2 connects the positive input of the low noise op-amp. The charge pump
output connects the negative input. This internal amplifier in cooperation with external components can provide
an active filter. The negative input is switchable to three input pins, to increase the flexibility in application. This
feature allows two separate active filters for different applications.
While the high current mode is activated LPHC output is switched on.
Low Noise CMOS Op-amp
1.7.7
The aim of IF counter is to measure the intermediate frequency of the tuner for AM and FM mode. The input
signal for FM and AM upconversion is the same 10.7MHz IF level after limiter. AM 450KHz signal is coming from
IF Counter Block
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| TDA7512F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FM car-radio tuner IC with intelligent selectivity system (ISS) |
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