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參數(shù)資料
| 型號： | TDA7343D |
| 廠商： | 意法半導體 |
| 英文描述： | DIGITALLY CONTROLLED AUDIO PROCESSOR |
| 中文描述： | 數(shù)控音頻處理器 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 100K |
| 代理商： | TDA7343D |
Figure 4:
Timing Diagram of I
2
CBUS
Figure 3:
Data Validity on the I
2
CBUS
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7343 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externallyconnected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledgebit. The MSB is transferredfirst.
Acknowledge
The master (
μ
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAlineis stableLOWduringthisclockpulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmissionwithout Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
μ
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreasesthe noise immunity.
Figure 5:
Acknowledgeon the I
2
CBUS
TDA7343
6/14
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| TDA7344 | DIGITAL CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
| TDA7344P | DIGITAL CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
| TDA7344S | DIGITAL CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
| TDA7345 | DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
| TDA7345D | DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TDA7344 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
| TDA7344P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
| TDA7344S | 制造商:STMicroelectronics 功能描述: 制造商:STMicroelectronics 功能描述:TONE/VOLUME/BALANCE CONTROL, 42 Pin, Plastic, SDIP |
| TDA7345 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
| TDA7345D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
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