參數(shù)資料
型號(hào): TDA7333
廠商: 意法半導(dǎo)體
英文描述: RDS/RBDS PROCESSOR
中文描述: 鐵路發(fā)展策略/無(wú)線廣播數(shù)據(jù)處理器
文件頁(yè)數(shù): 12/21頁(yè)
文件大小: 656K
代理商: TDA7333
TDA7333
12/21
Note : when changing the interrupt mode, one has to
perform a reset of the module (i.e set the bit “ar_res” at
one)
(3) qu[3..0] is a counter of the quality bit information coming
from the RDS demodulator. It is counting the number of bits
which are marked as bad by the demodulator. Only those bits
are allowed to be corrected. Thus the quality bit counter indi-
cates the maximum possible number of bits being corrected.
interrupt bit. It is set to one on every programmed interrupt. It
is reset by reading rds_int register.
interrupt source
itsrc[2:0] select the interrupt source (1)
synchronization information.
1: the module is already synchronized.
0: the module is synchronizing
It is used to force a resynchronization. If it is set to one, the
RDS modules are forced to resynchronization state.
The bit is automatically reset. So it is always read as zero.
RDS block.
if 1, one block has been detected
rds_int and rds_bd_ctrl write order (
when in SPI mode
)
1: rds_int and rds_bd_ctrl are updated with data shifted in.
0: rds_int and rds_bd_ctrl are not updated.
It indicates if the error correction was successfull.
1: the syndrome was zero after the error correction.
0: the syndrome did not become zero and therefore the
correction was not successfull.
1: a block E is detected.This indicates a paging block
which is defined in the RBDS specification used in the
united states of America.
0: an ordinary RDS block A, B, C, c′or D is detected, or no
valid syndrome was found.
bit 0 of block counter (2)
bit 1 of block counter (2)
bit 0 of quality counter
(3)
bit 1 of quality counter
(3)
bit 2 of quality counter
(3)
bit 3 of quality counter
(3)
bt name
access
bt 7
bt 0
bt 1
bt 2
bt 3
bt 4
bt 5
bt 6
r
r/w
r
r/w
r
r/w
r/w
r/w
itsrc0
int
ar_res
bne
itsrc1
synch
write
rese vaue
0
0
0
0
0
0
0
0
itsrc2
(1)
itsrc2
0
0
0
0
itsrc1
interrupt source
itsrc0
bock B
bock D
TA
TAEON
bock A
no interrupt
RDSBock
0
1
0
0
1
1
1
1
1
1
0
1
0
1
1
0
1
rds_nt
bit name
access
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
r
r
r
r
r
r
r
r
synz
e
qu0
qu3
qu1
qu2
blk1
blk0
blk1
1
0
0
0
blk0
block A
block name
block D
1
block C,C'
0
block B
1
1
(2)
reset value
0
0
0
0
0
0
0
0
rds_qu
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