參數(shù)資料
型號: TDA7331
廠商: 意法半導體
英文描述: SINGLE CHIP RDS DEMODULATOR+ FILTER
中文描述: 單片RDS解調(diào)器過濾器
文件頁數(shù): 4/7頁
文件大?。?/td> 56K
代理商: TDA7331
OUTPUT TIMING
The RDS (1187.5Hz) output clock on RDCL line
is synchronizedto the incoming data.
According to the internal PLL lock condition data
change can result on the falling or on the rising
clock edge. (see Fig. 1)
Whichever clock edge is used by the decoder
(rising or falling edge) the data will remain valid
for 416.7
μ
sec after the clock transition.
OSCILLATOR CONTROLS (FSEL, OSEL)
Three different crystal frequencies can be used.
The adaption of the internal clock divider to the
external crystal is achieved via the input pin
FSEL. See the followings table for reference:
Crystal
4.332MHz
8.664MHz
17.328MHz
FSEL
(pin configuration)
connected to GND or open
connected toVs
external resistor of 100K to Vs
A special mode is introduced to reduceEMI. With
pin OSEL connected to GND the internal oscilla-
tor is switched off and an external sinusoidal fre-
quency could be applied on OSCIN. The peak to
peak voltage of this signal can be reduced down
to 60mV.
In this mode the frequency selection via FSEL is
still active.
Suggested values of C1 and C2 are shown in the
following table:
Crystal
4.332MHz
8.664MHz
17.328MHz
C1
27pF
27pF
27pF
C2
47pF
-
-
Figure 1. RDS timing diagram
CLOCK
LINE
DATA
LINE
TDA7331
4/7
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