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參數(shù)資料
| 型號： | TDA7326D |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | AM-FM RADIO FREQUENCY SYNTHESIZER |
| 中文描述： | 上午調(diào)頻射頻合成器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 184K |
| 代理商： | TDA7326D |
2.0 GENERAL DESCRIPTION
This circuit contains a frequency synthesizer and
a loop filter for an FM and AM radio tuning sys-
tem. Only a V
CO
is required to build a complete
PLLsystem.
For FM and SW application, the counter works in
a two stagesconfiguration.
The first stage is a swallow counter with a four
modulus(:32/33/64/65)precounter.
The second stage is an 8-bit programmable
counter.
For LW and MW application, a 14-bit programma-
ble counteris available.
The circuit receives the scaling factors for the pro-
grammable counters and the values of the refer-
ence frequencies via a three line serial bus inter-
face.
The reference frequencyis generatedby a 4MHz
XTAL oscillator followed by the referencedivider.
An external oscillator (f = 4MHz) can be used in-
stead of the internal one; it must be connectedto
OSCIN (pin7).
The reference step-frequency is 1 or 2.5kHz for
AM. For FM mode a step frequency of 12.5 and
25kHz can be selected.
The circuit checks the format of the received data
words.
Valid data in the interface shift register are stored
automatically in buffer registers at the end of
transmission.
The output signals of the phase detector are
switching the programmable current sources.
Their currents are integrated in the loop filter to a
DC voltage.The values of the current sources are
programmable by two bits also received via the
serial bus.
The loop filter amplifier is supplied by a separate
positive power supply, to minimize the noise in-
duced by the digitalpart of the system.
3.2.2 CONTROL ANDSTATUS REGISTERS
RegisterConfiguration
The loopgain can be set fordifferent conditions.
After a power on reset, all registers are reset to
zero andthe standbymode is activated.
In standby mode, oscillator, reference counter,
AM input and FM input are stopped. The power
consumptionis reduced to a minimum.
3.0 DETAILED DESCRIPTION OF THE PLL
FREQUENCY SYNTHESIZER
3.1 INPUT AMPLIFIERS
The signals applied on AM and FM input are am-
plified to get a logic level in order to drive the fre-
quency dividers.
3.1.1 Input Impedance
The typical input impedance: for the FM input
is 200
and for AM inputis 1.4k
.
3.1.2 Input sensitivity
(seeFigures 1a and 1b).
3.2 DATAAND CONTROL REGISTER
3.2.1 Register Location
The data registers (bit2...bit7) for the control
register and the data registers PC7...PC0,
SC5...SC0 for the counters are organized in
four words, identified by two address bits (bit 7
and bit 6), bit 7 is the firstbit to be sent by the
controller, bit0 is the last one. The order and
the number of the bytes to be transmitted is
free of choice. The modification of the
PC7...PC0 registers is valid for the internal
counters only after transmission of byte 4
(SC5...SC0)
.
ADDRESS BITS
DATA BITS
BYTE
Function
byte 1
byte 2
byte 3
byte 4
MSB-BIT 7
adr 0
0
0
1
1
BIT 6
adr 1
0
1
0
1
BIT 5
data 0
test 0
PC7
PC5
SC5
BIT 4
data 1
test 1
PC6
PC4
SC4
BIT 3
data 2
test 2
LPF1/2
PC3
SC3
BIT 2
data 3
SOUT
CURR 1
PC2
SC2
BIT 1
data 4
CURR2
SWM/DIR
PC1
SC1
LSB BIT 0
data 5
f
REF
AM/FM
PC0
SC0
REGISTER NAME
SWM/DIR
AM/FM
f
REF
CURR1
CURR2
LPF1/LPF2
SOUT
FUNCTION
Swallow direct-mode switch 1 = SWM, 0 = DIR
AM - FM band switch 1=AM, 0 = FM
Selection of reference frequency (see table 3.4)
Current select of change pump
Current select of change pump
Loop filter input select1= I
PF1
, 0 = I
PF2
Switch output condition 1=output high,0 = output low
TDA7326
5/16
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