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參數(shù)資料
| 型號： | TDA4686 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Video processor with automatic cut-off control |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-117-1, MO-015AH, DIP-28 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 145K |
| 代理商： | TDA4686 |
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1997 Jun 23
8
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4686
A
UTO
-
INCREMENT
The auto-increment format enables quick slave receiver
initialization by one transmission, when the I
2
C-bus control
bit BREN = 0 (see control register bits of Table 1).
If BREN = 1 auto-increment is not possible.
If the auto-increment format is selected, the MAD byte is
followed by a SAD byte and by the data bytes of
consecutive subaddresses (see Fig.6).
All subaddresses from 00H to 0FH are automatically
incremented, the subaddress counter wraps round from
0FH to 00H. Reserved subaddresses 07H, 08H, 09H,
0BH, 0EH and 0FH are treated as legal but have no effect.
Subaddresses outside the range 00H and 0FH are not
acknowledged by the device.
Subaddresses are stored in the TDA4686 to address the
following parameters and functions (see Table 1):
Brightness adjust
Saturation adjust
Contrast adjust
Hue control voltage
RGB gain adjust
Peak drive limiting adjust
Control register functions.
The data bytes D7 to D0 (see Table 1) provide the data of
the parameters and functions for video processing.
C
ONTROL REGISTER
1
NMEN (NTSC Matrix Enable):
0 = PAL/SECAM matrix
1 = NTSC matrix.
BREN (Buffer Register Enable):
0 = new data is executed as soon as it is received
1 = data is stored in buffer registers and is transferred to
the data registers during the next vertical blanking
interval.
The I
2
C-bus receiver does not accept any new data until
this data is transferred into the data registers.
SC5 (SandCastle 5 V):
0 = 3-level sandcastle pulse
1 = 2-level (5 V) sandcastle pulse.
C
ONTROL REGISTER
2
FSON2 (Fast Switch 2 ON).
FSDIS2 (Fast Switch 2 Disable).
FSON1 (Fast Switch 1 ON).
FSDIS1 (Fast Switch 1 Disable).
The RGB input signals are selected by FSON2 and
FSON1 or FSW
2
and FSW
1
:
FSON2 has priority over FSON1
FSW
2
has priority over FSW
1
FSDIS1 and FSDIS2 disable FSW
1
and FSW
2
(see Table 2).
BCOF (Black level Control Off):
0 = automatic cut-off control enabled
1 = automatic cut-off control disabled; RGB outputs are
clamped to fixed DC levels.
When the supply voltage has dropped below
approximately 6.0 V (usually occurs when the TV receiver
is switched on or the supply voltage is interrupted) all data
and function bits are set to 01H.
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