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參數(shù)資料
| 型號： | TDA21302 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Multi-Phase PWM Controller for CPU Core Power Supply |
| 中文描述： | 多相PWM控制器，電源為CPU內(nèi)核電源 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 588K |
| 代理商： | TDA21302 |
CoreControl
TM
Page 16 of 25
DS-CoreControl-TDA21302
Protection and SS Function
For OVP, the TDA21302 detects the VCORE by VDIF pin voltage that is the output of the differential
amplifier. This is to eliminate the delay caused by the compensation network for faster and more
accurate detection. The trip point of OVP is 140% of the normal V
CORE
voltage level. The PWM outputs
are pulled low to turn on the Sync FET and to turn off the control FET while OVP is detected. The OVP
latch can only be reset by either VCC or DVD. The PGOOD trip point is set at the 92% of the normal
V
CORE
voltage level. The open drain PGOOD pin shall be pulled low while V
CORE
is lower than this point.
During the VID on the fly condition, there is nothing able to change the status of the PGOOD.
Soft-start circuit generates a ramp by charging an external capacitor with a 13uA constant current
source after the POR of IC is active. The pulse width of PWM signal and V
CORE
are clamped by rising
ramp to reduce the inrush current and protect the power devices.
Over-current protection trip point is internally set at around 100uA for each channel. OCP is triggered if
one channel S/H current signal. Controller forces PWM output latched at high impedance to turn off both
control and Sync FETs in the power stage and initial the hiccup mode protection. The SS pin voltage is
pulled low with a 13uA current after it is less than 90% VCC. The converter restarts after SS pin voltage
is lower than 0,2V. Three times of OCP disable the converter and only release the latch by POR acts.
CH1 : V
ADJ
CH2 : Short Circuit Current
CH3 : V
CORE
CH4 : V
SS
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