
Version 2.0
11
1 April 2001
TDA16850-2
(see Figure 1, Page4 and Figure 2, Page 5)
2.1 Off mode / Switch on process
At first the chip is in off mode. During switch on process
the supply voltage at VCC increases from 0 V to the
switch on threshold of V
VCC.
The total current
consumption of TDA 16850-2 is typ.100
A in this case.
When V
VCC exceeds the voltage of 21 V the chip can be
activated by an optocoupler current pulse higher than
50
A (typ.) and 10 s (typ.) duration.
2.2 Startup Mode
Entering startup mode the internal supply of TDA
16850-2 is switched on and all blocks are operable. In
the startup mode a current out of pin OPTO of 0
A <
|I
OPTO| < 2 mA is allowed. If there is no signal at pin
SYNC, the TDA 16850-2 generates gate pulses at a
rate of 20 kHz (typ.). The pulse width is first increased
during a soft start and then regulated for 11 V voltage
at Pin VREG.
2.3 Normal Mode
Normal mode can be entered from startup mode or
standby mode by increasing the opto current above 2
mA (typ.). In the normal mode the supply voltage must
be 8 V < V
VCC < 23 V typ. When there is no signal
present at SYNC, GATE clocks with a frequency of
typical f
OSC = 60 kHz (typ.). If there is a signal at SYNC
of
30 kHz < f
OSC < 130kHz
the internal oscillator is
synchronized automatically with this signal. If the
VREG voltage is higher than 11 V, the output pulse
width depends on the opto current. A higher opto
current means wider output pulses and a higher output
power of the power supply. Duty cycle minimum will be
achieved at a OPTO current of 2 mA (typ.).
2.4 Standby Mode
Standby mode is reached from either normal mode or
power down mode by adjusting the opto current within
160
A to 2 mA.
Voltage V
VREG will then be regulated to typ. 11 V. The
Oscillator frequency in standby mode is typ. 20 kHz. A
signal at pin SYNC is also evaluated in standby mode
and the oscillator is synchronized accordingly.
Standby mode can be quit to move to normal mode,
power down mode, or to move to protection mode.
In the standby mode the supply to the chip can be
switched over from pin VCC to pin VREG. The switch
is a current limiting switching transistor. It’s switched on
when V
VCC drops below typ. 10 V in normal mode.
When V
VREG is greater than VVCC the chip is now
supplied via V
VREG. At the same time the internal control
of the duty cycle at GATE is set so that there is typically
a voltage of 11 V at pin VREG. At VCC there is then a
voltage of typ. 9.5 V. The current at pin OPTO must
stay between 160
A < |I
OPTO| < 2 mA.
2.5 Power down Mode
At power down mode GATE will be disabled. The
power down mode is entered when the OPTO input
current is less than 160
A (typ.), after the IC has been
in the normal mode before.
2.6 Protection Mode
All failure modes will disable GATE. This is the
protection mode, which is latched and VCC and SST
will be discharged by internal transistors. Protection
mode can only be left through the off mode if V
VCC is
below 7.5 V (typ.).
2.7 Protection Circuitry
2.7.1 Over Current
The voltage at pin CS will be sensed by a comparator.
Until the voltage at pin CS is more than 1,2V (typ.) the
duty cycle will be reduced by discharging Pin SST by a
internal transistor.
2.7.2 Short Circuit
In case of a secondary short circuit, GATE will be
disabled as long as the voltage at pin CS is more than
1,5 V (typ.).
2.7.3 Failure Modes
The error message of the failure functions are stored in
a latch after a delay of typ. 70
s. GATE then will be
disabled. The latch is reset again when the chip is in off
mode .
2.7.3.1 Mains Undervoltage
A circuit checks the rise of the ramp singal at pin CS
for minimum slew rate.
2.7.3.2 IC Supply Overvoltage
A circuit checks the voltage at pin VCC.
2.7.3.3 IC Overtemperature
A thermal probe checks the temperature of the chip.
2.7.3.4 VREG Loop Failure
A circuit checks if the voltage at VREG is below 3 V
(typ.) and the voltage at pin SST have reached 2,6V
(typ.).
2.7.3.5 IC SupplyUndervoltage
A comparator checks the voltage at VCC.