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參數(shù)資料
| 型號： | TDA10085HT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Single chip DVB-S/DSS channel receiver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 93K |
| 代理商： | TDA10085HT |
2001 Aug 31
11
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
10 APPLICATION INFORMATION
handbook, full pagewidth
8
TDA10085HT
VREFP
VREFN
VAGC
30
15
51-54
59-62
12
28
29
33
32
2
1
XIN
XOUT
DO[7-0]
50
OCLK
49
DEN
48
UNCOR
47
PSYNC
SDA-0
SCL-0
SCL
SDA
MGU428
VIN2
GND
14
13
VIN1
PLL
LO
from
LNB
90
°
PHASE
SHIFT
MIXER
×
MIXER
×
The TDA10085 can receive a 4 MHz clock signal delivered by the PLL synthesizer, or can generate the sampling clock from a crystal connected
between XIN and XOUT.
Bypass capacitors (0.1
μ
F) should be placed close to ADC voltage references VREFP and VREFN.
Fig.3 Front-end receiver schematic.
handbook, full pagewidth
8
TDA10085
TUNER
channel I
VIN1
VAGC
30
15
51-54
59-62
12
28
29
33
32
63
21
CTRL1
22K
MPEG2
transport
stream
DO[7-0]
SDA-0
SCL-0
SCL
SDA
MGU429
VIN2
channel Q
LNB
LNB SUPPLY
GENERATION
Fig.4 Typical use of CTRL1 and 22K outputs.
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