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參數(shù)資料
| 型號： | TDA10023HT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT-357-1, TQFP-64 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大小： | 101K |
| 代理商： | TDA10023HT |
9397 750 14559
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 April 2005
7 of 20
Philips Semiconductors
TDA10023HT
Single chip DVB-C/MCNS channel receiver
VDDD3
7
S
digital core supply voltage 1.8 V
VSSD3
8
G
digital core ground
AGCTUN
9
O/OD
First PWM encoded output signal for AGC tuner. This signal is
typically fed to the AGC amplier through a single RC network.
The maximum signal frequency on VAGC output is XIN/16.
AGC information can be refreshed every 512 ADC samples.
IICDIV
10
I
IICDIV allows to select the frequency of the I2C-bus internal
system clock, depending on the crystal frequency. Internal
I2C-bus clock is a division of XIN by 4IICDIV.
AGCIF
11
O/OD
Second PWM encoded output signal for AGC IF. This signal is
typically fed to the AGC amplier through a single RC network.
The maximum signal frequency on VAGC output is XIN/16.
AGC information can be refreshed every 512 ADC samples.
But AGCIF can also be congured to output a PWM signal,
which value can be programmed through the I2C-bus interface
(see register PWMREF, index 34h).
SADDR
12
I
Two I2C-bus addresses are implemented in the TDA10023HT
chip. One address regarding all the TDA10023HT registers
except JQAM registers, and a second one dedicated to the
JQAM lter registers only.
SADDR is the LSB of the 2 I2C-bus addresses. The MSBs are
internally set to 000110 (all registers except JQAM) and 000111
(only JQAM). Therefore the 2 complete I2C-bus addresses are
(MSB to LSB):
0, 0, 0, 1, 1, 0, SADDR (core registers)
0, 0, 0, 1, 1, 1, SADDR (JQAM registers)
n.c.
13
not connected
VDDD2
14
S
digital pad supply voltage 3.3 V
VSSD2
15
G
digital pad ground
CLRB
16
I
The CLRB input is asynchronous and active LOW, and clears
the TDA10023HT. When CLRB goes LOW, the circuit
immediately enters its RESET mode and normal operation will
resume 4 XIN falling edges later after CLRB returned HIGH.
The I2C-bus register contents are all initialized to their default
values. The minimum width of CLRB at LOW level is 4 XIN
clock periods.
SCL
17
I
I2C-bus clock input. SCL should nominally be a square wave
with a maximum frequency of 400 kHz. SCL is generated by the
system I2C-bus master.
SDA
18
I/OD
SDA is a bidirectional signal. It is the serial input/output of the
I2C-bus internal block. A pull-up resistor (typically 4.7 k
) must
be connected between SDA and VDDD2 (or 5 V) for proper
operation (open-drain output).
SDAT
19
I/OD
SDAT is equivalent to SDA I/O of TDA10023HT but can be
3-stated by I2C-bus programming. It is actually the output of a
switch controlled by parameter BYPIIC of register TEST (index
0Fh). SDAT is an open-drain output and therefore requires an
external pull-up resistor.
Table 3:
Pin description …continued
Symbol
Pin
Type [1] Description
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| TDA10023HT/C1,518 | 制造商:Entropic Communications 功能描述:935273244518-R43 |
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| TDA10025HN/C1,551 | 功能描述:調(diào)節(jié)器/解調(diào)器 DUAL CBL DEMODULATOR RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| TDA10025HN/C1,557 | 功能描述:調(diào)節(jié)器/解調(diào)器 DUAL CBL DEMODULATOR RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
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