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| 型號(hào)： | TCS59SM804BFT-75 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動(dòng)態(tài)RAM) |
| 中文描述： | 1,600 × 4Banks × 4Bits同步DRAM（4組1,600 × 4位同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 31/49頁(yè) |
| 文件大?。?/td> | 2423K |
| 代理商： | TCS59SM804BFT-75 |
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TC59SM816/08/04BFT/BFTL-70,-75,-80
2000-03-14 31/49
Operation Mode
Table 1 shows the truth table for the operation commands.
Table 1. Truth Table (Note (1) and (2) )
Command
Device State CKE
n-1
CKE
n
DQM
(5)
BS0,
BS1
A10
A12,
A11,
A9~A0
CS
RAS
CAS
WE
Bank Activate
Idle
(3)
H
X
X
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active
(3)
H
X
X
V
L
V
L
H
L
L
Write with Auto Precharge
Active
(3)
H
X
X
V
H
V
L
H
L
L
Read
Active
(3)
H
X
X
V
L
V
L
H
L
H
Read with Auto Precharge
Active
(3)
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst stop
Active
(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto-Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self-Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
H
X
X
X
Self-Refresh Exit
Idle
(Self Refresh)
L
H
X
X
X
X
L
H
H
X
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
H
X
X
X
Power Down Mode Entry
Idle/Active
(6)
H
L
X
X
X
X
L
H
H
X
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
H
X
X
X
Power Down Mode Exit
Any
(Power Down)
L
H
X
X
X
X
L
H
H
X
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Write/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
Note 1. V
=
Valid, X
=
Don’t Care, L
=
Low level, H
=
High level
2. CKE
n
signal is input level when commands are issued.
CKE
n-1
signal is input level one clock cycle before the commands are issued.
3. These are state designated by the BS0, BS1 signals.
4. Device state is Full Page Burst operation.
5. LDQM, UDQM (TC59SM816BFT/BFTL)
6. Power Down Mode can not entry in the burst cycle.
When this command assert in the burst cycle, device state is clock suspend mode.
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